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Searched refs:I2C_ADAP_HWNR (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/include/configs/
H A Dstrider.h408 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
409 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
410 #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \
411 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
413 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
414 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
415 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
419 #define I2C_FPGA_IDX I2C_ADAP_HWNR
425 if (I2C_ADAP_HWNR > 7) \
H A Dhrcon.h387 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
388 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
389 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
394 if (I2C_ADAP_HWNR > 7) \
/openbmc/u-boot/drivers/i2c/
H A Dihs_i2c.c40 if (I2C_ADAP_HWNR & 0x10) \
41 FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
43 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
47 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
53 if (I2C_ADAP_HWNR & 0x10) \
54 FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
56 FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
60 FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
/openbmc/u-boot/include/
H A Di2c.h667 #define I2C_ADAP_HWNR (I2C_ADAP->hwadapnr) macro