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Searched refs:GICR_CTLR (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/tools/testing/selftests/kvm/include/aarch64/
H A Dgic_v3.h42 #define GICR_CTLR 0x000 macro
/openbmc/u-boot/arch/arm/include/asm/
H A Dgic.h55 #define GICR_CTLR 0x0000 macro
/openbmc/linux/tools/testing/selftests/kvm/lib/aarch64/
H A Dgic_v3.c48 while (readl(redist_base + GICR_CTLR) & GICR_CTLR_RWP) { in gicv3_gicr_wait_for_rwp()
/openbmc/qemu/hw/intc/
H A Darm_gicv3_kvm.c366 kvm_gicr_access(s, GICR_CTLR, ncpu, &reg, true); in kvm_arm_gicv3_put()
530 kvm_gicr_access(s, GICR_CTLR, ncpu, &reg, false); in kvm_arm_gicv3_get()
H A Darm_gicv3_redist.c351 case GICR_CTLR: in gicr_readl()
488 case GICR_CTLR: in gicr_writel()
H A Dgicv3_internal.h88 #define GICR_CTLR 0x0000 macro
/openbmc/linux/drivers/irqchip/
H A Dirq-gic-v3-its.c3010 val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR); in allocate_lpi_tables()
3091 val = readl_relaxed(rbase + GICR_CTLR); in its_cpu_init_lpis()
3166 val = readl_relaxed(rbase + GICR_CTLR); in its_cpu_init_lpis()
3168 writel_relaxed(val, rbase + GICR_CTLR); in its_cpu_init_lpis()
5205 val = readl_relaxed(rbase + GICR_CTLR); in redist_disable_lpis()
5229 writel_relaxed(val, rbase + GICR_CTLR); in redist_disable_lpis()
5239 while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) { in redist_disable_lpis()
5254 if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) { in redist_disable_lpis()
H A Dirq-gic-v3.c1064 u32 ctlr = readl_relaxed(ptr + GICR_CTLR); in __gic_update_rdist_properties()
/openbmc/linux/include/linux/irqchip/
H A Darm-gic-v3.h114 #define GICR_CTLR GICD_CTLR macro
/openbmc/linux/arch/arm64/kvm/vgic/
H A Dvgic-mmio-v3.c681 REGISTER_DESC_WITH_LENGTH(GICR_CTLR,