10ae76531SDavid Feng #ifndef __GIC_H__ 20ae76531SDavid Feng #define __GIC_H__ 316212b59SAndre Przywara 40ae76531SDavid Feng /* Register offsets for the ARM generic interrupt controller (GIC) */ 516212b59SAndre Przywara 616212b59SAndre Przywara #define GIC_DIST_OFFSET 0x1000 716212b59SAndre Przywara #define GIC_CPU_OFFSET_A9 0x0100 816212b59SAndre Przywara #define GIC_CPU_OFFSET_A15 0x2000 90ae76531SDavid Feng 100ae76531SDavid Feng /* Distributor Registers */ 110ae76531SDavid Feng #define GICD_CTLR 0x0000 120ae76531SDavid Feng #define GICD_TYPER 0x0004 130ae76531SDavid Feng #define GICD_IIDR 0x0008 140ae76531SDavid Feng #define GICD_STATUSR 0x0010 150ae76531SDavid Feng #define GICD_SETSPI_NSR 0x0040 160ae76531SDavid Feng #define GICD_CLRSPI_NSR 0x0048 170ae76531SDavid Feng #define GICD_SETSPI_SR 0x0050 180ae76531SDavid Feng #define GICD_CLRSPI_SR 0x0058 190ae76531SDavid Feng #define GICD_SEIR 0x0068 200ae76531SDavid Feng #define GICD_IGROUPRn 0x0080 210ae76531SDavid Feng #define GICD_ISENABLERn 0x0100 220ae76531SDavid Feng #define GICD_ICENABLERn 0x0180 230ae76531SDavid Feng #define GICD_ISPENDRn 0x0200 240ae76531SDavid Feng #define GICD_ICPENDRn 0x0280 250ae76531SDavid Feng #define GICD_ISACTIVERn 0x0300 260ae76531SDavid Feng #define GICD_ICACTIVERn 0x0380 270ae76531SDavid Feng #define GICD_IPRIORITYRn 0x0400 280ae76531SDavid Feng #define GICD_ITARGETSRn 0x0800 290ae76531SDavid Feng #define GICD_ICFGR 0x0c00 300ae76531SDavid Feng #define GICD_IGROUPMODRn 0x0d00 310ae76531SDavid Feng #define GICD_NSACRn 0x0e00 320ae76531SDavid Feng #define GICD_SGIR 0x0f00 330ae76531SDavid Feng #define GICD_CPENDSGIRn 0x0f10 340ae76531SDavid Feng #define GICD_SPENDSGIRn 0x0f20 350ae76531SDavid Feng #define GICD_IROUTERn 0x6000 360ae76531SDavid Feng 370ae76531SDavid Feng /* Cpu Interface Memory Mapped Registers */ 3816212b59SAndre Przywara #define GICC_CTLR 0x0000 3916212b59SAndre Przywara #define GICC_PMR 0x0004 400ae76531SDavid Feng #define GICC_BPR 0x0008 41ba6a1698SAndre Przywara #define GICC_IAR 0x000C 42ba6a1698SAndre Przywara #define GICC_EOIR 0x0010 430ae76531SDavid Feng #define GICC_RPR 0x0014 440ae76531SDavid Feng #define GICC_HPPIR 0x0018 450ae76531SDavid Feng #define GICC_ABPR 0x001c 460ae76531SDavid Feng #define GICC_AIAR 0x0020 470ae76531SDavid Feng #define GICC_AEOIR 0x0024 480ae76531SDavid Feng #define GICC_AHPPIR 0x0028 490ae76531SDavid Feng #define GICC_APRn 0x00d0 500ae76531SDavid Feng #define GICC_NSAPRn 0x00e0 510ae76531SDavid Feng #define GICC_IIDR 0x00fc 520ae76531SDavid Feng #define GICC_DIR 0x1000 5316212b59SAndre Przywara 54*c71645adSDavid Feng /* ReDistributor Registers for Control and Physical LPIs */ 55*c71645adSDavid Feng #define GICR_CTLR 0x0000 56*c71645adSDavid Feng #define GICR_IIDR 0x0004 57*c71645adSDavid Feng #define GICR_TYPER 0x0008 58*c71645adSDavid Feng #define GICR_STATUSR 0x0010 59*c71645adSDavid Feng #define GICR_WAKER 0x0014 60*c71645adSDavid Feng #define GICR_SETLPIR 0x0040 61*c71645adSDavid Feng #define GICR_CLRLPIR 0x0048 62*c71645adSDavid Feng #define GICR_SEIR 0x0068 63*c71645adSDavid Feng #define GICR_PROPBASER 0x0070 64*c71645adSDavid Feng #define GICR_PENDBASER 0x0078 65*c71645adSDavid Feng #define GICR_INVLPIR 0x00a0 66*c71645adSDavid Feng #define GICR_INVALLR 0x00b0 67*c71645adSDavid Feng #define GICR_SYNCR 0x00c0 68*c71645adSDavid Feng #define GICR_MOVLPIR 0x0100 69*c71645adSDavid Feng #define GICR_MOVALLR 0x0110 70*c71645adSDavid Feng 71*c71645adSDavid Feng /* ReDistributor Registers for SGIs and PPIs */ 72*c71645adSDavid Feng #define GICR_IGROUPRn 0x0080 73*c71645adSDavid Feng #define GICR_ISENABLERn 0x0100 74*c71645adSDavid Feng #define GICR_ICENABLERn 0x0180 75*c71645adSDavid Feng #define GICR_ISPENDRn 0x0200 76*c71645adSDavid Feng #define GICR_ICPENDRn 0x0280 77*c71645adSDavid Feng #define GICR_ISACTIVERn 0x0300 78*c71645adSDavid Feng #define GICR_ICACTIVERn 0x0380 79*c71645adSDavid Feng #define GICR_IPRIORITYRn 0x0400 80*c71645adSDavid Feng #define GICR_ICFGR0 0x0c00 81*c71645adSDavid Feng #define GICR_ICFGR1 0x0c04 82*c71645adSDavid Feng #define GICR_IGROUPMODRn 0x0d00 83*c71645adSDavid Feng #define GICR_NSACRn 0x0e00 84*c71645adSDavid Feng 85*c71645adSDavid Feng /* Cpu Interface System Registers */ 86*c71645adSDavid Feng #define ICC_IAR0_EL1 S3_0_C12_C8_0 87*c71645adSDavid Feng #define ICC_IAR1_EL1 S3_0_C12_C12_0 88*c71645adSDavid Feng #define ICC_EOIR0_EL1 S3_0_C12_C8_1 89*c71645adSDavid Feng #define ICC_EOIR1_EL1 S3_0_C12_C12_1 90*c71645adSDavid Feng #define ICC_HPPIR0_EL1 S3_0_C12_C8_2 91*c71645adSDavid Feng #define ICC_HPPIR1_EL1 S3_0_C12_C12_2 92*c71645adSDavid Feng #define ICC_BPR0_EL1 S3_0_C12_C8_3 93*c71645adSDavid Feng #define ICC_BPR1_EL1 S3_0_C12_C12_3 94*c71645adSDavid Feng #define ICC_DIR_EL1 S3_0_C12_C11_1 95*c71645adSDavid Feng #define ICC_PMR_EL1 S3_0_C4_C6_0 96*c71645adSDavid Feng #define ICC_RPR_EL1 S3_0_C12_C11_3 97*c71645adSDavid Feng #define ICC_CTLR_EL1 S3_0_C12_C12_4 98*c71645adSDavid Feng #define ICC_CTLR_EL3 S3_6_C12_C12_4 99*c71645adSDavid Feng #define ICC_SRE_EL1 S3_0_C12_C12_5 100*c71645adSDavid Feng #define ICC_SRE_EL2 S3_4_C12_C9_5 101*c71645adSDavid Feng #define ICC_SRE_EL3 S3_6_C12_C12_5 102*c71645adSDavid Feng #define ICC_IGRPEN0_EL1 S3_0_C12_C12_6 103*c71645adSDavid Feng #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 104*c71645adSDavid Feng #define ICC_IGRPEN1_EL3 S3_6_C12_C12_7 105*c71645adSDavid Feng #define ICC_SEIEN_EL1 S3_0_C12_C13_0 106*c71645adSDavid Feng #define ICC_SGI0R_EL1 S3_0_C12_C11_7 107*c71645adSDavid Feng #define ICC_SGI1R_EL1 S3_0_C12_C11_5 108*c71645adSDavid Feng #define ICC_ASGI1R_EL1 S3_0_C12_C11_6 109*c71645adSDavid Feng 1100ae76531SDavid Feng #endif /* __GIC_H__ */ 111