| /openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | config.h | 48 #define GICD_BASE 0x06000000 macro
141 #define GICD_BASE 0x06000000 macro
210 #define GICD_BASE 0x06000000 macro
273 #define GICD_BASE 0x01401000 macro
301 #define GICD_BASE 0x01401000 macro
332 #define GICD_BASE 0x01410000 macro
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| /openbmc/u-boot/arch/arm/mach-rmobile/ |
| H A D | lowlevel_init_gen3.S | 26 ldr x0, =GICD_BASE
33 ldr x0, =GICD_BASE
40 ldr x0, =GICD_BASE
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| /openbmc/u-boot/include/configs/ |
| H A D | sun50i.h | 14 #define GICD_BASE 0x1c81000 macro
17 #define GICD_BASE 0x3021000 macro
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| H A D | vexpress_aemv8a.h | 83 #define GICD_BASE (0x2f000000) macro
89 #define GICD_BASE (0x2f000000) macro
92 #define GICD_BASE (0x2C010000) macro
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| H A D | meson64.h | 12 #define GICD_BASE 0xffc01000 macro
15 #define GICD_BASE 0xc4301000 macro
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| H A D | thunderx_88xx.h | 39 #define GICD_BASE (0x801000000000) macro
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| H A D | rcar-gen3-common.h | 28 #define GICD_BASE 0xF1010000 macro
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| H A D | hikey.h | 44 #define GICD_BASE 0xf6801000 macro
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| H A D | xilinx_versal.h | 18 #define GICD_BASE 0xF9000000 macro
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| H A D | s32v234evb.h | 17 #define GICD_BASE 0x7D001000 macro
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| H A D | xilinx_zynqmp.h | 19 #define GICD_BASE 0xF9010000 macro
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| /openbmc/u-boot/arch/arm/cpu/armv7/sunxi/ |
| H A D | psci.c | 26 #define GICD_BASE (SUNXI_GIC400_BASE + GIC_DIST_OFFSET) macro
284 writel(BIT(16) | 15, GICD_BASE + GICD_SGIR); in psci_cpu_off()
297 clrbits_le32(GICD_BASE + GICD_IGROUPRn, BIT(15)); in psci_arch_init()
300 writeb(0, GICD_BASE + GICD_IPRIORITYRn + 15); in psci_arch_init()
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| /openbmc/u-boot/arch/arm/cpu/armv8/ |
| H A D | start.S | 294 ldr x0, =GICD_BASE
301 ldr x0, =GICD_BASE
348 ldr x0, =GICD_BASE
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| /openbmc/u-boot/arch/arm/include/asm/arch-tegra186/ |
| H A D | tegra.h | 9 #define GICD_BASE 0x03881000 /* Generic Int Cntrlr Distrib */ macro
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| /openbmc/u-boot/arch/arm/include/asm/arch-tegra210/ |
| H A D | tegra.h | 10 #define GICD_BASE 0x50041000 /* Generic Int Cntrlr Distrib */ macro
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| /openbmc/u-boot/arch/arm/mach-socfpga/include/mach/ |
| H A D | base_addr_s10.h | 40 #define GICD_BASE 0xfffc1000 macro
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| /openbmc/u-boot/arch/arm/mach-snapdragon/include/mach/ |
| H A D | sysmap-apq8016.h | 10 #define GICD_BASE (0x0b000000) macro
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| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/ |
| H A D | fdt.c | 203 reg[0] = cpu_to_fdt64(GICD_BASE); in fdt_fixup_gic()
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| H A D | lowlevel.S | 31 ldr x0, =GICD_BASE
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