Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12, v00.04.11, v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01, v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13, v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03, v00.02.02, v00.02.01, v2019.07, v00.02.00, v2019.04 |
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66c433ed |
| 31-Mar-2019 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
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cfb3e102 |
| 22-Mar-2019 |
Tom Rini <trini@konsulko.com> |
Merge branch '2019-03-22-master-imports'
- Don't attempt to write to ext4 volumes with the metadata_csum feature we don't support - Correct how we build dtb files. - Fix regression on SPL_FIT with
Merge branch '2019-03-22-master-imports'
- Don't attempt to write to ext4 volumes with the metadata_csum feature we don't support - Correct how we build dtb files. - Fix regression on SPL_FIT with FIT_IMAGE_TINY - Minor TI platform fixes
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ef331e36 |
| 20-Feb-2019 |
Alexander Graf <agraf@suse.de> |
armv8: Disable exception vectors in SPL by default
Commit 1416e2d2253 ("armv8: make SPL exception vectors optional") had a typo in it which effectively disabled exception handling in SPL code always
armv8: Disable exception vectors in SPL by default
Commit 1416e2d2253 ("armv8: make SPL exception vectors optional") had a typo in it which effectively disabled exception handling in SPL code always.
Since nobody complained, I guess we may as well disable exception handling in SPL always by default.
So fix the bug to make the config option effective, but disable exception handling in SPL by default. This gets us to the same functionality as before by default, but with much less code included in the binary.
Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Matthias Brugger <mbrugger@suse.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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1416e2d2 |
| 24-Jul-2018 |
Andre Przywara <andre.przywara@arm.com> |
armv8: make SPL exception vectors optional
Even though the exception vector table is a fundamental part of the ARM architecture, U-Boot mostly does not make real use of it, except when crash dumping
armv8: make SPL exception vectors optional
Even though the exception vector table is a fundamental part of the ARM architecture, U-Boot mostly does not make real use of it, except when crash dumping. But having it in takes up quite some space, partly due to the architectural alignment requirement of 2KB. Since we don't take special care of that, the compiler adds a more or less random amount of padding space, which increases the image size quite a bit, especially for the SPL.
On a typical Allwinner build this is around 1.5KB of padding, plus 1KB for the vector table (mostly padding space again), then some extra code to do the actual handling. This amounts to almost 10% of the maximum image size, which is quite a lot for a pure debugging feature.
Add a Kconfig symbol to allow the exception vector table to be left out of the build for the SPL. For now this is "default y" for everyone, but specific defconfigs, platforms or .config files can opt out here at will, to mitigate the code size pressure we see for some SPLs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Revision tags: v2018.07 |
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83d290c5 |
| 06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So
SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one.
Signed-off-by: Tom Rini <trini@konsulko.com>
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Revision tags: v2018.03 |
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18af9657 |
| 12-Jan-2018 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-tegra
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Revision tags: v2018.01 |
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8163faf9 |
| 03-Jan-2018 |
Stephen Warren <swarren@nvidia.com> |
ARMv8: add optional Linux kernel image header
Allow placing a Linux kernel image header at the start of the U-Boot binary. This is useful since the image header reports the amount of memory (BSS and
ARMv8: add optional Linux kernel image header
Allow placing a Linux kernel image header at the start of the U-Boot binary. This is useful since the image header reports the amount of memory (BSS and similar) that U-Boot needs to use, but that isn't part of the binary size. This can be used by the code that loads U-Boot into memory to determine where to load U-Boot, based on other users of memory.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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6bf63422 |
| 11-Jan-2018 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq
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ab0ab54e |
| 27-Dec-2017 |
Alison Wang <b18965@freescale.com> |
armv8: Implement workaround for Cortex-A53 erratum 855873
855873: An eviction might overtake a cache clean operation Workaround: The erratum can be avoided by upgrading cache clean by address operat
armv8: Implement workaround for Cortex-A53 erratum 855873
855873: An eviction might overtake a cache clean operation Workaround: The erratum can be avoided by upgrading cache clean by address operations to cache clean and invalidate operations. For Cortex-A53 r0p3 and later release, this can be achieved by setting CPUACTLR.ENDCCASCI to 1.
This patch is to implement the workaround for this erratum.
Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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Revision tags: v2017.11 |
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49e93875 |
| 02-Nov-2017 |
Stephen Warren <swarren@nvidia.com> |
arm64: support running at addr other than linked to
This is required in the case where U-Boot is typically loaded and run at a particular address, but for some reason the RAM at that location is not
arm64: support running at addr other than linked to
This is required in the case where U-Boot is typically loaded and run at a particular address, but for some reason the RAM at that location is not available, e.g. due to memory fragmentation loading other boot binaries or firmware, splitting an SMP complex between various different OSs without using e.g. the EL2 second-stage page tables to hide the memory asignments, or due to known ECC failures.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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541f538f |
| 03-Jun-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq
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399e2bb6 |
| 15-May-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Make U-Boot EL2 safe
When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carrie
armv8: layerscape: Make U-Boot EL2 safe
When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first.
Signed-off-by: York Sun <york.sun@nxp.com>
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9ad7147b |
| 26-Apr-2017 |
Dinh Nguyen <dinguyen@kernel.org> |
armv8: minor fix to comment for enabling SMPEN bit
The SMPEN bit is located in the cpuectlr_el1 register and not the cpuactlr_el1 register. Adjust the comment accordingly and also fix a spelling err
armv8: minor fix to comment for enabling SMPEN bit
The SMPEN bit is located in the cpuectlr_el1 register and not the cpuactlr_el1 register. Adjust the comment accordingly and also fix a spelling error.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> CC: Mingkai Hu <mingkai.hu@nxp.com> CC: Gong Qianyu <Qianyu.Gong@nxp.com> CC: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> CC: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> CC: York Sun <york.sun@nxp.com> CC: Albert Aribaud <albert.u.boot@aribaud.net> CC: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: York Sun <york.sun@nxp.com>
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0675f992 |
| 19-Jan-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq
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7c5e1feb |
| 16-Jan-2017 |
Alison Wang <b18965@freescale.com> |
armv8: aarch64: Fix the warning about x1-x3 nonzero issue
For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for ar
armv8: aarch64: Fix the warning about x1-x3 nonzero issue
For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero.
Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Alexander Graf <agraf@suse.de> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: York Sun <york.sun@nxp.com>
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3aec452e |
| 06-Jan-2017 |
Mingkai Hu <mingkai.hu@nxp.com> |
armv8: Enable CPUECTLR.SMPEN for coherency
For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is set. The SMPEN bit should be set before enabling the data cache. If not enabled, the
armv8: Enable CPUECTLR.SMPEN for coherency
For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is set. The SMPEN bit should be set before enabling the data cache. If not enabled, the cache is not coherent with other cores and data corruption could occur.
For A57/A72, SMPEN bit enables the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster. This bit should be set before enabling the caches and MMU, or performing any cache and TLB maintenance operations.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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4b105f6c |
| 27-Dec-2016 |
Oded Gabbay <oded.gabbay@gmail.com> |
armv8: fix #if around spin-table code in start.S
Using CONFIG_IS_ENABLED() doesn't work in SPL. This patch replaces the only occurrence of CONFIG_IS_ENABLED() in start.S to a regular #if defined().
armv8: fix #if around spin-table code in start.S
Using CONFIG_IS_ENABLED() doesn't work in SPL. This patch replaces the only occurrence of CONFIG_IS_ENABLED() in start.S to a regular #if defined(). It also adds "&& !defined(CONFIG_SPL_BUILD)" to that #if statement because the spin-table code can't currently work in SPL, and the spin-table file isn't even compiled in SPL.
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
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0b840433 |
| 10-Jan-2017 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-sunxi
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ce62e57f |
| 02-Jan-2017 |
Andre Przywara <andre.przywara@arm.com> |
ARM: boot0 hook: remove macro, include whole header file
For prepending some board specific header area to U-Boot images we were so far including a header file with a macro definition containing the
ARM: boot0 hook: remove macro, include whole header file
For prepending some board specific header area to U-Boot images we were so far including a header file with a macro definition containing the actual header specification. This works fine if there are just a few statements and if there is only one alternative. However adding more complex code quickly gets messy with this approach, so let's just drop that intermediate macro and let the #include actually insert the code directly. This converts the callers and the callees, but doesn't change anything at this point.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Steve Rae <steve.rae@raedomain.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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a5168a59 |
| 02-Jan-2017 |
Andre Przywara <andre.przywara@arm.com> |
armv8: move reset branch into boot hook
The boot0 hook we have so far is applied _after_ the initial branch to the "reset" entry point. An upcoming change requires even this branch to be changed, so
armv8: move reset branch into boot hook
The boot0 hook we have so far is applied _after_ the initial branch to the "reset" entry point. An upcoming change requires even this branch to be changed, so we apply the hook macro at the earliest point, and have the branch in the hook file as well. This is no functional change at this point, just refactoring to simplify upcoming patches.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
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2d221489 |
| 29-Nov-2016 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
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ed77ccd0 |
| 25-Nov-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq
Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts: arch/arm/Kconfig
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ec6617c3 |
| 09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: Support loading 32-bit OS in AArch32 execution state
To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel.
The architecture informat
armv8: Support loading 32-bit OS in AArch32 execution state
To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel.
The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically.
Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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9f84da8d |
| 21-Jul-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-tegra
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0e2b5350 |
| 18-Jul-2016 |
Stephen Warren <swarren@nvidia.com> |
ARM: Add save_boot_params for ARMv8
Implement a hook to allow boards to save boot-time CPU state for later use. When U-Boot is chain-loaded by another bootloader, CPU registers may contain useful in
ARM: Add save_boot_params for ARMv8
Implement a hook to allow boards to save boot-time CPU state for later use. When U-Boot is chain-loaded by another bootloader, CPU registers may contain useful information such as system configuration information. This feature mirrors the equivalent ARMv7 feature.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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