183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 28faeab93SChin Liang See /* 38faeab93SChin Liang See * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> 48faeab93SChin Liang See */ 58faeab93SChin Liang See 68faeab93SChin Liang See #ifndef _SOCFPGA_S10_BASE_HARDWARE_H_ 78faeab93SChin Liang See #define _SOCFPGA_S10_BASE_HARDWARE_H_ 88faeab93SChin Liang See 9*641f7470SLey Foon Tan #define SOCFPGA_CCU_ADDRESS 0xf7000000 108faeab93SChin Liang See #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 118faeab93SChin Liang See #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 128faeab93SChin Liang See #define SOCFPGA_SDR_ADDRESS 0xf8011000 13*641f7470SLey Foon Tan #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 148faeab93SChin Liang See #define SOCFPGA_SMMU_ADDRESS 0xfa000000 158faeab93SChin Liang See #define SOCFPGA_MAILBOX_ADDRESS 0xffa30000 168faeab93SChin Liang See #define SOCFPGA_UART0_ADDRESS 0xffc02000 178faeab93SChin Liang See #define SOCFPGA_UART1_ADDRESS 0xffc02100 188faeab93SChin Liang See #define SOCFPGA_SPTIMER0_ADDRESS 0xffc03000 198faeab93SChin Liang See #define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100 208faeab93SChin Liang See #define SOCFPGA_SYSTIMER0_ADDRESS 0xffd00000 218faeab93SChin Liang See #define SOCFPGA_SYSTIMER1_ADDRESS 0xffd00100 22*641f7470SLey Foon Tan #define SOCFPGA_L4WD0_ADDRESS 0xffd00200 23*641f7470SLey Foon Tan #define SOCFPGA_L4WD1_ADDRESS 0xffd00300 24*641f7470SLey Foon Tan #define SOCFPGA_L4WD2_ADDRESS 0xffd00400 25*641f7470SLey Foon Tan #define SOCFPGA_L4WD3_ADDRESS 0xffd00500 268faeab93SChin Liang See #define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000 278faeab93SChin Liang See #define SOCFPGA_GTIMER_NSEC_ADDRESS 0xffd02000 288faeab93SChin Liang See #define SOCFPGA_CLKMGR_ADDRESS 0xffd10000 298faeab93SChin Liang See #define SOCFPGA_RSTMGR_ADDRESS 0xffd11000 308faeab93SChin Liang See #define SOCFPGA_SYSMGR_ADDRESS 0xffd12000 318faeab93SChin Liang See #define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000 32*641f7470SLey Foon Tan #define SOCFPGA_FIREWALL_L4_PER 0xffd21000 33*641f7470SLey Foon Tan #define SOCFPGA_FIREWALL_L4_SYS 0xffd21100 34*641f7470SLey Foon Tan #define SOCFPGA_FIREWALL_SOC2FPGA 0xffd21200 35*641f7470SLey Foon Tan #define SOCFPGA_FIREWALL_LWSOC2FPGA 0xffd21300 36*641f7470SLey Foon Tan #define SOCFPGA_FIREWALL_TCU 0xffd21400 378faeab93SChin Liang See #define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 388faeab93SChin Liang See #define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 398faeab93SChin Liang See #define SOCFPGA_OCRAM_ADDRESS 0xffe00000 408faeab93SChin Liang See #define GICD_BASE 0xfffc1000 418faeab93SChin Liang See #define GICC_BASE 0xfffc2000 428faeab93SChin Liang See 438faeab93SChin Liang See #endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */ 44