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Searched refs:FP_DIV0 (Results 1 – 7 of 7) sorted by relevance

/openbmc/qemu/linux-user/loongarch64/
H A Dcpu_loop.c57 } else if (GET_FP_CAUSE(env->fcsr0) & FP_DIV0) { in cpu_loop()
/openbmc/qemu/linux-user/mips/
H A Dcpu_loop.c172 } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_DIV0) { in cpu_loop()
/openbmc/qemu/target/loongarch/
H A Dcpu.h83 #define FP_DIV0 8 macro
/openbmc/qemu/target/mips/
H A Dcpu.h96 #define FP_DIV0 8 macro
/openbmc/qemu/target/loongarch/tcg/
H A Dfpu_helper.c50 ret |= FP_DIV0; in ieee_ex_to_loongarch()
/openbmc/qemu/target/mips/tcg/
H A Dfpu_helper.c194 mips_xcpt |= FP_DIV0; in ieee_to_mips_xcpt()
H A Dmsa_helper.c6205 mips_xcpt |= FP_DIV0; in ieee_to_mips_xcpt_msa()
6272 (mips_exception_flags & (FP_INVALID | FP_DIV0)) == 0) { in update_msacsr()