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Searched refs:DRAM_TYPE_DDR3 (Results 1 – 14 of 14) sorted by relevance

/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c459 if (para->dram_type == DRAM_TYPE_DDR3) { in mctl_channel_init()
572 if (para->dram_type == DRAM_TYPE_DDR3) { in mctl_channel_init()
598 if (para->dram_type == DRAM_TYPE_DDR3) { in mctl_channel_init()
629 if (para->dram_type != DRAM_TYPE_DDR3) in mctl_channel_init()
663 if (para->dram_type == DRAM_TYPE_DDR3) { in mctl_channel_init()
717 if (para->dram_type == DRAM_TYPE_DDR3) in mctl_channel_init()
749 if (para->dram_type == DRAM_TYPE_DDR3) in mctl_channel_init()
869 .dram_type = DRAM_TYPE_DDR3, in sunxi_dram_init()
H A Ddram_sun8i_a83t.c133 if (para->dram_type == DRAM_TYPE_DDR3) { in auto_set_timing_para()
337 if (para->dram_type == DRAM_TYPE_DDR3) in mctl_channel_init()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sun9i.h207 ((type == DRAM_TYPE_DDR3) ? MCTL_MSTR_DEVICETYPE_DDR3 : \
214 ((type == DRAM_TYPE_DDR3) ? MCTL_MSTR_BURSTLENGTH8 : \
273 #define DRAM_TYPE_DDR3 3 macro
H A Ddram_sun8i_a83t.h205 #define DRAM_TYPE_DDR3 3 macro
/openbmc/u-boot/include/dt-bindings/mrc/
H A Dquark.h33 #define DRAM_TYPE_DDR3 0 macro
/openbmc/linux/drivers/memory/tegra/
H A Dtegra124-emc.c288 DRAM_TYPE_DDR3 = 0, enumerator
629 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()
724 if (emc->dram_type == DRAM_TYPE_DDR3 && in tegra_emc_prepare_timing_change()
751 if (emc->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF) in tegra_emc_prepare_timing_change()
757 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()
766 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()
774 if (emc->dram_type == DRAM_TYPE_DDR3) { in tegra_emc_prepare_timing_change()
857 if (emc->dram_type == DRAM_TYPE_DDR3 && in tegra_emc_complete_timing_change()
H A Dtegra30-emc.c226 DRAM_TYPE_DDR3, enumerator
648 if (dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_ON) { in emc_prepare_timing_change()
701 if (dram_type == DRAM_TYPE_DDR3) { in emc_prepare_timing_change()
731 if (dram_type == DRAM_TYPE_DDR3) in emc_prepare_timing_change()
736 if (dram_type == DRAM_TYPE_DDR3) { in emc_prepare_timing_change()
1172 case DRAM_TYPE_DDR3: in emc_setup_hw()
H A Dtegra210-emc-cc-r21021.c641 if (dram_type == DRAM_TYPE_DDR3) in tegra210_emc_r21021_set_clock()
879 else if (dram_type == DRAM_TYPE_DDR3) in tegra210_emc_r21021_set_clock()
1042 dram_type == DRAM_TYPE_DDR3 && opt_zcal_en_cc && in tegra210_emc_r21021_set_clock()
1512 } else if (dram_type == DRAM_TYPE_DDR3) { in tegra210_emc_r21021_set_clock()
1552 } else if (dram_type == DRAM_TYPE_DDR3) { in tegra210_emc_r21021_set_clock()
1695 else if (dram_type == DRAM_TYPE_DDR3) in tegra210_emc_r21021_set_clock()
H A Dtegra210-emc.h881 #define DRAM_TYPE_DDR3 0 macro
/openbmc/u-boot/arch/x86/include/asm/arch-braswell/fsp/
H A Dfsp_configs.h55 #define DRAM_TYPE_DDR3 0 macro
/openbmc/u-boot/arch/x86/include/asm/arch-baytrail/fsp/
H A Dfsp_configs.h71 #define DRAM_TYPE_DDR3 0 macro
/openbmc/u-boot/arch/x86/cpu/braswell/
H A Dfsp_configs.c90 "fsp,memory-type", DRAM_TYPE_DDR3); in update_fsp_configs()
/openbmc/u-boot/arch/x86/dts/
H A Dgalileo.dts53 dram-type = <DRAM_TYPE_DDR3>;
H A Dcherryhill.dts173 fsp,memory-type = <DRAM_TYPE_DDR3>;