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Searched refs:DPLL_MODE_MASK (Results 1 – 14 of 14) sorted by relevance

/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk322x.c182 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff, in rkclk_pll_get_rate()
338 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rk322x_ddr_set_clk()
342 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rk322x_ddr_set_clk()
H A Dclk_rk3188.c149 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
159 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
H A Dclk_rk3288.c205 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
215 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
H A Dclk_rk3036.c181 0xffffffff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xffffffff, in rkclk_pll_get_rate()
H A Dclk_rk3128.c250 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK, in rkclk_pll_get_rate()
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3188.h164 DPLL_MODE_MASK = 3, enumerator
H A Dcru_rk3036.h93 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, enumerator
H A Dcru_rk322x.h100 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, enumerator
H A Dcru_rk3128.h102 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, enumerator
H A Dcru_rk3288.h198 DPLL_MODE_MASK = CRU_MODE_MASK << DPLL_MODE_SHIFT, enumerator
/openbmc/u-boot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c332 rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, in rkdclk_init()
351 rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, in rkdclk_init()
/openbmc/linux/drivers/gpu/drm/gma500/
H A Dpsb_intel_reg.h235 #define DPLL_MODE_MASK (3 << 26) macro
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_display.c3868 switch (dpll & DPLL_MODE_MASK) { in i9xx_crtc_clock_get()
3880 "mode\n", (int)(dpll & DPLL_MODE_MASK)); in i9xx_crtc_clock_get()
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_reg.h1437 #define DPLL_MODE_MASK (3 << 26) macro