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Searched refs:DPIO_PHY1 (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c1124 MMIO_D(BXT_PHY_CTL_FAMILY(DPIO_PHY1)); in iterate_bxt_mmio()
1140 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1)); in iterate_bxt_mmio()
1141 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1)); in iterate_bxt_mmio()
1142 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1)); in iterate_bxt_mmio()
1143 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1)); in iterate_bxt_mmio()
1144 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1)); in iterate_bxt_mmio()
1145 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1)); in iterate_bxt_mmio()
1146 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1)); in iterate_bxt_mmio()
1147 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1)); in iterate_bxt_mmio()
1148 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1)); in iterate_bxt_mmio()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_power_well.c1328 if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY1]) in assert_chv_phy_status()
1329 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | in assert_chv_phy_status()
1330 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | in assert_chv_phy_status()
1331 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); in assert_chv_phy_status()
1375 phy_status |= PHY_POWERGOOD(DPIO_PHY1); in assert_chv_phy_status()
1378 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) in assert_chv_phy_status()
1379 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); in assert_chv_phy_status()
1382 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) in assert_chv_phy_status()
1383 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); in assert_chv_phy_status()
1386 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) in assert_chv_phy_status()
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H A Dintel_dpio_phy.c167 .rcomp_phy = DPIO_PHY1,
175 [DPIO_PHY1] = {
189 .rcomp_phy = DPIO_PHY1,
197 [DPIO_PHY1] = {
209 .rcomp_phy = DPIO_PHY1,
665 return DPIO_PHY1; in vlv_dig_port_to_phy()
H A Dintel_dpio_phy.h25 DPIO_PHY1, enumerator
H A Dintel_display_power.c1766 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | in chv_phy_control_init()
1769 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); in chv_phy_control_init()
1819 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); in chv_phy_control_init()
1822 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); in chv_phy_control_init()
1824 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); in chv_phy_control_init()
1826 dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = false; in chv_phy_control_init()
1828 dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = true; in chv_phy_control_init()
H A Dintel_display_power_map.c480 .bxt.phy = DPIO_PHY1,
584 .bxt.phy = DPIO_PHY1,
/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Dmmio.c266 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= in intel_vgpu_reset_mmio()
270 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= in intel_vgpu_reset_mmio()
H A Ddisplay.c237 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= in emulate_monitor_status_change()
240 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30); in emulate_monitor_status_change()
269 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= in emulate_monitor_status_change()
271 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |= in emulate_monitor_status_change()
H A Dhandlers.c547 phy = DPIO_PHY1; in bxt_vgpu_get_dp_bitrate()
1886 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= in bxt_gt_disp_pwron_write()
1888 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= in bxt_gt_disp_pwron_write()
2756 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT, in init_bxt_mmio_info()
2773 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT, in init_bxt_mmio_info()
2775 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT, in init_bxt_mmio_info()