1df0566a6SJani Nikula /* SPDX-License-Identifier: MIT */ 2df0566a6SJani Nikula /* 3df0566a6SJani Nikula * Copyright © 2019 Intel Corporation 4df0566a6SJani Nikula */ 5df0566a6SJani Nikula 6df0566a6SJani Nikula #ifndef __INTEL_DPIO_PHY_H__ 7df0566a6SJani Nikula #define __INTEL_DPIO_PHY_H__ 8df0566a6SJani Nikula 9df0566a6SJani Nikula #include <linux/types.h> 10df0566a6SJani Nikula 112461bdb3SJani Nikula enum pipe; 12df0566a6SJani Nikula enum port; 13df0566a6SJani Nikula struct drm_i915_private; 14df0566a6SJani Nikula struct intel_crtc_state; 152461bdb3SJani Nikula struct intel_digital_port; 16df0566a6SJani Nikula struct intel_encoder; 17df0566a6SJani Nikula 18*99417adbSJani Nikula enum dpio_channel { 19*99417adbSJani Nikula DPIO_CH0, 20*99417adbSJani Nikula DPIO_CH1, 21*99417adbSJani Nikula }; 22*99417adbSJani Nikula 23*99417adbSJani Nikula enum dpio_phy { 24*99417adbSJani Nikula DPIO_PHY0, 25*99417adbSJani Nikula DPIO_PHY1, 26*99417adbSJani Nikula DPIO_PHY2, 27*99417adbSJani Nikula }; 28*99417adbSJani Nikula 29df0566a6SJani Nikula void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, 30df0566a6SJani Nikula enum dpio_phy *phy, enum dpio_channel *ch); 315f5ada0bSVille Syrjälä void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder, 325f5ada0bSVille Syrjälä const struct intel_crtc_state *crtc_state); 33df0566a6SJani Nikula void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy); 34df0566a6SJani Nikula void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy); 35df0566a6SJani Nikula bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, 36df0566a6SJani Nikula enum dpio_phy phy); 37df0566a6SJani Nikula bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, 38df0566a6SJani Nikula enum dpio_phy phy); 39df0566a6SJani Nikula u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count); 40df0566a6SJani Nikula void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder, 41df0566a6SJani Nikula u8 lane_lat_optim_mask); 42df0566a6SJani Nikula u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder); 43df0566a6SJani Nikula 442461bdb3SJani Nikula enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port); 452461bdb3SJani Nikula enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port); 462461bdb3SJani Nikula enum dpio_channel vlv_pipe_to_channel(enum pipe pipe); 472461bdb3SJani Nikula 48df0566a6SJani Nikula void chv_set_phy_signal_level(struct intel_encoder *encoder, 49a621860aSVille Syrjälä const struct intel_crtc_state *crtc_state, 50df0566a6SJani Nikula u32 deemph_reg_value, u32 margin_reg_value, 51df0566a6SJani Nikula bool uniq_trans_scale); 52df0566a6SJani Nikula void chv_data_lane_soft_reset(struct intel_encoder *encoder, 53df0566a6SJani Nikula const struct intel_crtc_state *crtc_state, 54df0566a6SJani Nikula bool reset); 55df0566a6SJani Nikula void chv_phy_pre_pll_enable(struct intel_encoder *encoder, 56df0566a6SJani Nikula const struct intel_crtc_state *crtc_state); 57df0566a6SJani Nikula void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, 58df0566a6SJani Nikula const struct intel_crtc_state *crtc_state); 59df0566a6SJani Nikula void chv_phy_release_cl2_override(struct intel_encoder *encoder); 60df0566a6SJani Nikula void chv_phy_post_pll_disable(struct intel_encoder *encoder, 61df0566a6SJani Nikula const struct intel_crtc_state *old_crtc_state); 62df0566a6SJani Nikula 63df0566a6SJani Nikula void vlv_set_phy_signal_level(struct intel_encoder *encoder, 64a621860aSVille Syrjälä const struct intel_crtc_state *crtc_state, 65df0566a6SJani Nikula u32 demph_reg_value, u32 preemph_reg_value, 66df0566a6SJani Nikula u32 uniqtranscale_reg_value, u32 tx3_demph); 67df0566a6SJani Nikula void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, 68df0566a6SJani Nikula const struct intel_crtc_state *crtc_state); 69df0566a6SJani Nikula void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, 70df0566a6SJani Nikula const struct intel_crtc_state *crtc_state); 71df0566a6SJani Nikula void vlv_phy_reset_lanes(struct intel_encoder *encoder, 72df0566a6SJani Nikula const struct intel_crtc_state *old_crtc_state); 73df0566a6SJani Nikula 74df0566a6SJani Nikula #endif /* __INTEL_DPIO_PHY_H__ */ 75