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Searched refs:DB_PRINT (Results 1 – 17 of 17) sorted by relevance

/openbmc/qemu/hw/ssi/
H A Dxilinx_spi.c39 #define DB_PRINT(...) do { \ macro
44 #define DB_PRINT(...) macro
144 DB_PRINT("irq_change of state %u ISR:%x IER:%X\n", in xlx_spi_update_irq()
181 DB_PRINT("data tx:%x\n", tx); in spi_flush_txfifo()
183 DB_PRINT("data rx:%x\n", rx); in spi_flush_txfifo()
214 DB_PRINT("Read from empty FIFO!\n"); in spi_read()
236 DB_PRINT("addr=" HWADDR_FMT_plx " = %x\n", addr * 4, r); in spi_read()
248 DB_PRINT("addr=" HWADDR_FMT_plx " = %x\n", addr, value); in spi_write()
253 DB_PRINT("Invalid write to SRR %x\n", value); in spi_write()
268 DB_PRINT("DTR and master enabled\n"); in spi_write()
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H A Dstm32f2xx_spi.c41 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) macro
60 DB_PRINT("Data to send: 0x%x\n", s->spi_dr); in stm32f2xx_spi_transfer()
65 DB_PRINT("Data received: 0x%x\n", s->spi_dr); in stm32f2xx_spi_transfer()
73 DB_PRINT("Address: 0x%" HWADDR_PRIx "\n", addr); in stm32f2xx_spi_read()
122 DB_PRINT("Address: 0x%" HWADDR_PRIx ", Value: 0x%x\n", addr, value); in stm32f2xx_spi_write()
H A Dmss-spi.c43 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) macro
199 DB_PRINT("addr=0x%" HWADDR_PRIx " = 0x%" PRIx32, addr * 4, ret); in spi_read()
236 DB_PRINT("data tx:0x%" PRIx32, tx); in spi_flush_txfifo()
238 DB_PRINT("data rx:0x%" PRIx32, rx); in spi_flush_txfifo()
273 DB_PRINT("addr=0x%" HWADDR_PRIx " =0x%" PRIx32, addr, value); in spi_write()
/openbmc/qemu/hw/char/
H A Dstm32f2xx_usart.c43 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) macro
73 DB_PRINT("Dropping the chars\n"); in stm32f2xx_usart_receive()
82 DB_PRINT("Receiving: %c\n", s->usart_dr); in stm32f2xx_usart_receive()
106 DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr); in stm32f2xx_usart_read()
114 DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr); in stm32f2xx_usart_read()
146 DB_PRINT("Write 0x%" PRIx32 ", 0x%"HWADDR_PRIx"\n", value, addr); in stm32f2xx_usart_write()
H A Dcadence_uart.c39 #define DB_PRINT(...) do { \ macro
44 #define DB_PRINT(...) macro
425 DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); in uart_write()
504 DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c); in uart_read()
/openbmc/qemu/hw/timer/
H A Dstm32f2xx_timer.c43 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) macro
51 DB_PRINT("Interrupt\n"); in stm32f2xx_timer_interrupt()
64 DB_PRINT("PWM2 Duty Cycle: %d%%\n", in stm32f2xx_timer_interrupt()
83 DB_PRINT("Alarm set at: 0x%x\n", s->tim_cr1); in stm32f2xx_timer_set_alarm()
88 DB_PRINT("Alarm set in %d ticks\n", (int) ticks); in stm32f2xx_timer_set_alarm()
94 DB_PRINT("Wait Time: %" PRId64 " ticks\n", s->hit_time); in stm32f2xx_timer_set_alarm()
129 DB_PRINT("Read 0x%"HWADDR_PRIx"\n", offset); in stm32f2xx_timer_read()
187 DB_PRINT("Write 0x%x, 0x%"HWADDR_PRIx"\n", value, offset); in stm32f2xx_timer_write()
H A Da9gtimer.c48 #define DB_PRINT(...) DB_PRINT_L(0, ## __VA_ARGS__) macro
96 DB_PRINT("Compare event happened for CPU %d\n", i); in a9_gtimer_update()
101 DB_PRINT("Auto incrementing timer compare by %" in a9_gtimer_update()
118 DB_PRINT("scheduling qemu_timer to fire again in %" in a9_gtimer_update()
177 DB_PRINT("addr:%#x data:%#08" PRIx64 "\n", (unsigned)addr, ret); in a9_gtimer_read()
188 DB_PRINT("addr:%#x data:%#08" PRIx64 "\n", (unsigned)addr, value); in a9_gtimer_write()
242 DB_PRINT("CPU:%d:", id); in a9_gtimer_this_read()
254 DB_PRINT("CPU:%d:", id); in a9_gtimer_this_write()
H A Dcadence_ttc.c30 #define DB_PRINT(...) do { \ macro
35 #define DB_PRINT(...) macro
145 DB_PRINT("next timer event value: %09llx\n", in cadence_timer_run()
164 DB_PRINT("cpu time: %lld ns\n", (long long)old_time); in cadence_timer_sync()
202 DB_PRINT("\n"); in cadence_timer_tick()
285 DB_PRINT("addr: %08x data: %08x\n", (unsigned)offset, (unsigned)ret); in cadence_ttc_read()
294 DB_PRINT("addr: %08x data %08x\n", (unsigned)offset, (unsigned)value); in cadence_ttc_write()
H A Dmss-timer.c44 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) macro
129 DB_PRINT("timer=%d 0x%" HWADDR_PRIx "=0x%" PRIx32, timer, offset, in timer_read()
156 DB_PRINT("addr=0x%" HWADDR_PRIx " val=0x%" PRIx32 " (timer=%d)", offset, in timer_write()
H A Davr_timer16.c108 #define DB_PRINT(fmt, args...) /* Nothing */ macro
/openbmc/qemu/hw/net/
H A Dcadence_gem.c41 #define DB_PRINT(...) do {\ macro
462 DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); in print_gem_tx_desc()
463 DB_PRINT("bufaddr: 0x%08x\n", *desc); in print_gem_tx_desc()
464 DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); in print_gem_tx_desc()
465 DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); in print_gem_tx_desc()
466 DB_PRINT("last: %d\n", tx_desc_get_last(desc)); in print_gem_tx_desc()
467 DB_PRINT("length: %d\n", tx_desc_get_length(desc)); in print_gem_tx_desc()
642 DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); in phy_update_link()
669 DB_PRINT("can't receive - no enable\n"); in gem_can_receive()
683 DB_PRINT("can't receive - all the buffer descriptors are busy\n"); in gem_can_receive()
[all …]
/openbmc/qemu/hw/misc/
H A Dstm32f2xx_syscfg.c40 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) macro
60 DB_PRINT("0x%"HWADDR_PRIx"\n", addr); in stm32f2xx_syscfg_read()
92 DB_PRINT("0x%x, 0x%"HWADDR_PRIx"\n", value, addr); in stm32f2xx_syscfg_write()
H A Dzynq_slcr.c34 #define DB_PRINT(...) do { \ macro
332 DB_PRINT("RESET\n"); in zynq_slcr_reset_init()
515 DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx32 "\n", offset * 4, ret); in zynq_slcr_read()
525 DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx64 "\n", offset * 4, val); in zynq_slcr_write()
539 DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset, in zynq_slcr_write()
543 DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n", in zynq_slcr_write()
549 DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset, in zynq_slcr_write()
553 DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n", in zynq_slcr_write()
/openbmc/qemu/hw/dma/
H A Dxlnx-zynq-devcfg.c44 #define DB_PRINT(fmt, args...) do { \ macro
163 DB_PRINT("reading %x bytes from %x\n", btt, dmah->src_addr); in xlnx_zynq_devcfg_dma_go()
169 DB_PRINT("writing %x bytes from %x\n", btt, dmah->dest_addr); in xlnx_zynq_devcfg_dma_go()
176 DB_PRINT("dma operation finished\n"); in xlnx_zynq_devcfg_dma_go()
226 DB_PRINT("successful unlock\n"); in r_unlock_post_write()
258 DB_PRINT("dma transfer started; %d total transfers pending\n", in r_dma_dst_len_post_write()
/openbmc/qemu/hw/intc/
H A Dxlnx-zynqmp-ipi.c48 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) macro
148 DB_PRINT("Setting %s=%d\n", index_array_names[i], in xlnx_zynqmp_ipi_set_trig()
161 DB_PRINT("Setting %s=%d\n", index_array_names[i], in xlnx_zynqmp_ipi_set_obs()
171 DB_PRINT("irq=%d isr=%x mask=%x\n", in xlnx_zynqmp_ipi_update_irq()
280 DB_PRINT("IPI input irq[%d]=%d\n", n, level); in xlnx_zynqmp_ipi_handler()
291 DB_PRINT("OBS input irq[%d]=%d\n", n, level); in xlnx_zynqmp_obs_handler()
H A Dxlnx-pmu-iomod-intc.c48 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) macro
342 DB_PRINT("Setting IRQ output = %d\n", irq_out); in xlnx_pmu_io_irq_update()
/openbmc/qemu/hw/adc/
H A Dstm32f2xx_adc.c42 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) macro
105 DB_PRINT("Address: 0x%" HWADDR_PRIx "\n", addr); in stm32f2xx_adc_read()
176 DB_PRINT("Address: 0x%" HWADDR_PRIx ", Value: 0x%x\n", in stm32f2xx_adc_write()