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Searched refs:CWL (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dsddr3.c72 int CWL, CL, WR, DLL = 0, ODT = 0; in nvkm_sddr3_calc() local
82 CWL = ram->next->bios.timing_10_CWL; in nvkm_sddr3_calc()
88 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; in nvkm_sddr3_calc()
100 CWL = ramxlat(ramddr3_cwl, CWL); in nvkm_sddr3_calc()
103 if (CL < 0 || CWL < 0 || WR < 0) in nvkm_sddr3_calc()
118 ram->mr[2] |= (CWL & 0x07) << 3; in nvkm_sddr3_calc()
H A Dgddr3.c73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; in nvkm_gddr3_calc() local
77 CWL = ram->next->bios.timing_10_CWL; in nvkm_gddr3_calc()
85 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; in nvkm_gddr3_calc()
104 if (CL < 0 || CWL < 1 || CWL > 7 || WR < 0) in nvkm_gddr3_calc()
108 ram->mr[0] |= (CWL & 0x07) << 9; in nvkm_gddr3_calc()
H A Dramnv50.c86 switch ((!T(CWL)) * ram->base.type) { in nv50_ram_timing_calc()
88 T(CWL) = T(CL) - 1; in nv50_ram_timing_calc()
91 T(CWL) = ((cur2 & 0xff000000) >> 24) + 1; in nv50_ram_timing_calc()
98 timing[6] = (0x2d + T(CL) - T(CWL) + in nv50_ram_timing_calc()
100 T(CWL) << 8 | in nv50_ram_timing_calc()
101 (0x2f + T(CL) - T(CWL)); in nv50_ram_timing_calc()
104 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | in nv50_ram_timing_calc()
105 max_t(s8, T(CWL) - 2, 1) << 8 | in nv50_ram_timing_calc()
106 (0x2e + T(CL) - T(CWL)); in nv50_ram_timing_calc()
110 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in nv50_ram_timing_calc()
[all …]
H A Dramgt215.c362 switch ((!T(CWL)) * ram->base.type) { in gt215_ram_timing_calc()
364 T(CWL) = T(CL) - 1; in gt215_ram_timing_calc()
367 T(CWL) = ((cur2 & 0xff000000) >> 24) + 1; in gt215_ram_timing_calc()
375 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in gt215_ram_timing_calc()
377 (T(WTR) + 1 + T(CWL)) << 8 | in gt215_ram_timing_calc()
378 (5 + T(CL) - T(CWL)); in gt215_ram_timing_calc()
379 timing[2] = (T(CWL) - 1) << 24 | in gt215_ram_timing_calc()
393 max_t(u8, (T(CWL) + 6), (T(CL) + 2)) << 8 | in gt215_ram_timing_calc()
396 max_t(u8, 1, (6 - T(CL) + T(CWL))) << 8 | in gt215_ram_timing_calc()
397 (0x50 + T(CL) - T(CWL)); in gt215_ram_timing_calc()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c90 u32 CWL; member
361 u32 CWL = 0; in mctl_channel_init() local
438 CWL = para->cl_cwl_table[i].CWL; in mctl_channel_init()
440 debug("found CL/CWL: CL = %d, CWL = %d\n", CL, CWL); in mctl_channel_init()
445 if ((CL == 0) && (CWL == 0)) { in mctl_channel_init()
463 mr[2] = DDR3_MR2_TWL(CWL); in mctl_channel_init()
518 #define WR2PRE (MCTL_BL/2 + CWL + tWTR) in mctl_channel_init()
520 #define WR2RD (MCTL_BL/2 + CWL + tWTR) in mctl_channel_init()
525 #define RD2WR (CL + MCTL_BL/2 + 2 - CWL) in mctl_channel_init()
539 writel((MCTL_DIV2(CWL) << 24) | (MCTL_DIV2(CL) << 16) | in mctl_channel_init()
[all …]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2400/
H A Dplatform.S642 mov r1, r1, lsr #6 @ Set CWL
712 mov r1, r1, lsr #7 @ Set CWL
827 mov r1, r2, lsr #4 @ Set CWL