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Searched refs:CTS (Results 1 – 25 of 100) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_afmt.c51 static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq) in amdgpu_afmt_calc_cts() argument
82 *CTS = cts; in amdgpu_afmt_calc_cts()
85 *N, *CTS, freq); in amdgpu_afmt_calc_cts()
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-core/opencl/
H A Dopencl-cts_2024.08.08.bb1 SUMMARY = "OpenCL CTS"
2 DESCRIPTION = "OpenCL CTS test suite"
13 SRC_URI = "git://github.com/KhronosGroup/OpenCL-CTS.git;protocol=https;branch=main;lfs=0 \
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-venice-gw73xx-0x-rs232-rts.dtso5 * GW73xx RS232 with RTS/CTS hardware flow control:
8 * - UART4_RX becomes CTS
H A Dimx8mm-venice-gw72xx-0x-rs232-rts.dtso5 * GW72xx RS232 with RTS/CTS hardware flow control:
8 * - UART4_RX becomes CTS
H A Dimx8mq-hummingboard-pulse.dts166 * reconfigured to enable RTS/CTS on UART3
209 * Header. To use RTS/CTS on UART3 comment them out
/openbmc/linux/drivers/crypto/intel/keembay/
H A DKconfig31 bool "Support for Intel Keem Bay OCS AES/SM4 CTS HW acceleration"
35 AES/SM4 CBC with CTS mode hardware acceleration for use with
40 Intel does not recommend use of CTS mode with AES/SM4.
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-dhcom-drc02.dts23 * The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins.
24 * Therefore the UART RTS/CTS must be output on other DHCOM pins, see uart1
H A Dimx6ul-ccimx6ulsbcpro.dts62 /* CAN2 is multiplexed with UART2 RTS/CTS */
201 /* UART2 RTS/CTS muxed with CAN2 */
209 /* UART3 RTS/CTS muxed with CAN 1 */
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-netcom-plus-2xx.dts25 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) /* CTS */
38 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* CTS */
/openbmc/u-boot/cmd/aspeed/
H A DKconfig21 bool "ASPEED DP controller CTS"
/openbmc/u-boot/arch/x86/include/asm/arch-baytrail/
H A Diomap.h42 #define CTS (1 << 19) macro
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-graphics/deqp-runner/
H A Ddeqp-runner_0.20.2.bb1 SUMMARY = "A VK-GL-CTS/dEQP wrapper program to parallelize it across CPUs and report results agains…
/openbmc/linux/arch/arm/boot/dts/st/
H A Dste-dbx5x0-pinctrl.dtsi17 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
28 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
75 pins = "GPIO6_AF6"; /* CTS */
86 pins = "GPIO6_AF6"; /* CTS */
H A Dstm32mp157a-iot-box.dts57 /* Note: HW flow control is broken, hence using custom CTS/RTS gpios */
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-graphics/vk-gl-cts/
H A Dvulkan-cts_1.3.9.2.bb1 DESCRIPTION = "Vulkan CTS"
H A Dopengl-es-cts_3.2.11.0.bb1 DESCRIPTION = "OpenGL CTS"
/openbmc/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64-orangepi-win.dts382 /* On Pi-2 connector, RTS/CTS optional */
389 /* On Pi-2 connector, RTS/CTS optional */
396 /* On Pi-2 connector (labeled for SPI1), RTS/CTS optional */
H A Dsun50i-a64-pine64.dts285 /* On Wifi/BT connector, with RTS/CTS */
306 /* On Euler connector, RTS/CTS optional */
/openbmc/linux/Documentation/usb/
H A Diuu_phoenix.rst44 0=none, 1=CD, 2=!CD, 3=DSR, 4=!DSR, 5=CTS, 6=!CTS, 7=RING, 8=!RING (int)
/openbmc/linux/drivers/tty/
H A Dnozomi.c238 unsigned int CTS:1; member
299 unsigned int CTS:1; member
921 if (old_ctrl.CTS == 1 && ctrl_dl.CTS == 0) { in receive_flow_control()
926 } else if (old_ctrl.CTS == 0 && ctrl_dl.CTS == 1) { in receive_flow_control()
944 if (old_ctrl.CTS != ctrl_dl.CTS) in receive_flow_control()
1618 if (port->ctrl_dl.CTS) { in ntty_write()
1668 | (ctrl_dl->CTS ? TIOCM_CTS : 0); in ntty_tiocmget()
/openbmc/qemu/include/hw/char/
H A Dnrf51_uart.h39 FIELD(UART_INTEN, CTS, 0, 1)
/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dmicrochip,pic32-uart.txt14 - cts-gpios: CTS pin for UART
H A Dcirrus,clps711x-uart.txt11 - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dserial.txt14 CTS, RTS, DCD, DSR, DTR, and RI.
/openbmc/u-boot/arch/arm/dts/
H A Dsun50i-a64-orangepi-win.dts339 /* On Pi-2 connector, RTS/CTS optional */
346 /* On Pi-2 connector, RTS/CTS optional */
353 /* On Pi-2 connector (labeled for SPI1), RTS/CTS optional */

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