xref: /openbmc/linux/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c (revision ac8f933664c3a0e2d42f6ee9a2a6d25f87cb23f6)
1d38ceaf9SAlex Deucher /*
2d38ceaf9SAlex Deucher  * Copyright 2008 Advanced Micro Devices, Inc.
3d38ceaf9SAlex Deucher  * Copyright 2008 Red Hat Inc.
4d38ceaf9SAlex Deucher  * Copyright 2009 Christian König.
5d38ceaf9SAlex Deucher  *
6d38ceaf9SAlex Deucher  * Permission is hereby granted, free of charge, to any person obtaining a
7d38ceaf9SAlex Deucher  * copy of this software and associated documentation files (the "Software"),
8d38ceaf9SAlex Deucher  * to deal in the Software without restriction, including without limitation
9d38ceaf9SAlex Deucher  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10d38ceaf9SAlex Deucher  * and/or sell copies of the Software, and to permit persons to whom the
11d38ceaf9SAlex Deucher  * Software is furnished to do so, subject to the following conditions:
12d38ceaf9SAlex Deucher  *
13d38ceaf9SAlex Deucher  * The above copyright notice and this permission notice shall be included in
14d38ceaf9SAlex Deucher  * all copies or substantial portions of the Software.
15d38ceaf9SAlex Deucher  *
16d38ceaf9SAlex Deucher  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17d38ceaf9SAlex Deucher  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18d38ceaf9SAlex Deucher  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19d38ceaf9SAlex Deucher  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20d38ceaf9SAlex Deucher  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21d38ceaf9SAlex Deucher  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22d38ceaf9SAlex Deucher  * OTHER DEALINGS IN THE SOFTWARE.
23d38ceaf9SAlex Deucher  *
24d38ceaf9SAlex Deucher  * Authors: Christian König
25d38ceaf9SAlex Deucher  */
26d38ceaf9SAlex Deucher #include <linux/hdmi.h>
27d38ceaf9SAlex Deucher #include <linux/gcd.h>
28fdf2f6c5SSam Ravnborg 
29d38ceaf9SAlex Deucher #include <drm/amdgpu_drm.h>
30d38ceaf9SAlex Deucher #include "amdgpu.h"
31d38ceaf9SAlex Deucher 
32d38ceaf9SAlex Deucher static const struct amdgpu_afmt_acr amdgpu_afmt_predefined_acr[] = {
33d38ceaf9SAlex Deucher     /*	     32kHz	  44.1kHz	48kHz    */
34d38ceaf9SAlex Deucher     /* Clock      N     CTS      N     CTS      N     CTS */
35d38ceaf9SAlex Deucher     {  25175,  4096,  25175, 28224, 125875,  6144,  25175 }, /*  25,20/1.001 MHz */
36d38ceaf9SAlex Deucher     {  25200,  4096,  25200,  6272,  28000,  6144,  25200 }, /*  25.20       MHz */
37d38ceaf9SAlex Deucher     {  27000,  4096,  27000,  6272,  30000,  6144,  27000 }, /*  27.00       MHz */
38d38ceaf9SAlex Deucher     {  27027,  4096,  27027,  6272,  30030,  6144,  27027 }, /*  27.00*1.001 MHz */
39d38ceaf9SAlex Deucher     {  54000,  4096,  54000,  6272,  60000,  6144,  54000 }, /*  54.00       MHz */
40d38ceaf9SAlex Deucher     {  54054,  4096,  54054,  6272,  60060,  6144,  54054 }, /*  54.00*1.001 MHz */
41d38ceaf9SAlex Deucher     {  74176,  4096,  74176,  5733,  75335,  6144,  74176 }, /*  74.25/1.001 MHz */
42d38ceaf9SAlex Deucher     {  74250,  4096,  74250,  6272,  82500,  6144,  74250 }, /*  74.25       MHz */
43d38ceaf9SAlex Deucher     { 148352,  4096, 148352,  5733, 150670,  6144, 148352 }, /* 148.50/1.001 MHz */
44d38ceaf9SAlex Deucher     { 148500,  4096, 148500,  6272, 165000,  6144, 148500 }, /* 148.50       MHz */
45d38ceaf9SAlex Deucher };
46d38ceaf9SAlex Deucher 
47d38ceaf9SAlex Deucher 
48d38ceaf9SAlex Deucher /*
49d38ceaf9SAlex Deucher  * calculate CTS and N values if they are not found in the table
50d38ceaf9SAlex Deucher  */
amdgpu_afmt_calc_cts(uint32_t clock,int * CTS,int * N,int freq)51d38ceaf9SAlex Deucher static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq)
52d38ceaf9SAlex Deucher {
53d38ceaf9SAlex Deucher 	int n, cts;
54d38ceaf9SAlex Deucher 	unsigned long div, mul;
55d38ceaf9SAlex Deucher 
56d38ceaf9SAlex Deucher 	/* Safe, but overly large values */
57d38ceaf9SAlex Deucher 	n = 128 * freq;
58d38ceaf9SAlex Deucher 	cts = clock * 1000;
59d38ceaf9SAlex Deucher 
60d38ceaf9SAlex Deucher 	/* Smallest valid fraction */
61d38ceaf9SAlex Deucher 	div = gcd(n, cts);
62d38ceaf9SAlex Deucher 
63d38ceaf9SAlex Deucher 	n /= div;
64d38ceaf9SAlex Deucher 	cts /= div;
65d38ceaf9SAlex Deucher 
66d38ceaf9SAlex Deucher 	/*
67d38ceaf9SAlex Deucher 	 * The optimal N is 128*freq/1000. Calculate the closest larger
68d38ceaf9SAlex Deucher 	 * value that doesn't truncate any bits.
69d38ceaf9SAlex Deucher 	 */
70d38ceaf9SAlex Deucher 	mul = ((128*freq/1000) + (n-1))/n;
71d38ceaf9SAlex Deucher 
72d38ceaf9SAlex Deucher 	n *= mul;
73d38ceaf9SAlex Deucher 	cts *= mul;
74d38ceaf9SAlex Deucher 
75d38ceaf9SAlex Deucher 	/* Check that we are in spec (not always possible) */
76d38ceaf9SAlex Deucher 	if (n < (128*freq/1500))
777ca85295SJoe Perches 		pr_warn("Calculated ACR N value is too small. You may experience audio problems.\n");
78d38ceaf9SAlex Deucher 	if (n > (128*freq/300))
797ca85295SJoe Perches 		pr_warn("Calculated ACR N value is too large. You may experience audio problems.\n");
80d38ceaf9SAlex Deucher 
81d38ceaf9SAlex Deucher 	*N = n;
82d38ceaf9SAlex Deucher 	*CTS = cts;
83d38ceaf9SAlex Deucher 
84d38ceaf9SAlex Deucher 	DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n",
85d38ceaf9SAlex Deucher 		  *N, *CTS, freq);
86d38ceaf9SAlex Deucher }
87d38ceaf9SAlex Deucher 
amdgpu_afmt_acr(uint32_t clock)88d38ceaf9SAlex Deucher struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock)
89d38ceaf9SAlex Deucher {
90d38ceaf9SAlex Deucher 	struct amdgpu_afmt_acr res;
91d38ceaf9SAlex Deucher 	u8 i;
92d38ceaf9SAlex Deucher 
93d38ceaf9SAlex Deucher 	/* Precalculated values for common clocks */
94d38ceaf9SAlex Deucher 	for (i = 0; i < ARRAY_SIZE(amdgpu_afmt_predefined_acr); i++) {
95d38ceaf9SAlex Deucher 		if (amdgpu_afmt_predefined_acr[i].clock == clock)
96d38ceaf9SAlex Deucher 			return amdgpu_afmt_predefined_acr[i];
97d38ceaf9SAlex Deucher 	}
98d38ceaf9SAlex Deucher 
99d38ceaf9SAlex Deucher 	/* And odd clocks get manually calculated */
100d38ceaf9SAlex Deucher 	amdgpu_afmt_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000);
101d38ceaf9SAlex Deucher 	amdgpu_afmt_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100);
102d38ceaf9SAlex Deucher 	amdgpu_afmt_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000);
103*761964b7SMa Jun 	res.clock = clock;
104d38ceaf9SAlex Deucher 
105d38ceaf9SAlex Deucher 	return res;
106d38ceaf9SAlex Deucher }
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