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Searched refs:CPM (Results 1 – 25 of 28) sorted by relevance

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/openbmc/linux/Documentation/devicetree/bindings/powerpc/4xx/
H A Dcpm.txt1 PPC4xx Clock Power Management (CPM) node
9 - er-offset : All 4xx SoCs with a CPM controller have
10 one of two different order for the CPM
11 registers. Some have the CPM registers
18 in CPM will be set to turn off unused
22 in CPM will be set to turn off unused
23 devices. This is usually just CPM[CPU].
26 in CPM will be set on standby and
30 in CPM will be set on suspend (mem) and
/openbmc/linux/drivers/soc/fsl/qe/
H A DKconfig14 coprocessors on Freescale embedded CPUs (akin to CPM in older chips).
37 tristate "CPM TSA support"
39 depends on CPM1 || (CPM && COMPILE_TEST)
41 Freescale CPM Time Slot Assigner (TSA)
48 tristate "CPM QMC support"
50 depends on CPM1 || (FSL_SOC && CPM && COMPILE_TEST)
53 Freescale CPM QUICC Multichannel Controller
/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dcpm.txt7 * Root CPM node
22 * Properties common to multiple CPM/QE devices
25 to specify the device on which a CPM command operates.
38 The multi-user/dual-ported RAM is expressed as a bus under the CPM node.
47 CPM-side offsets with pointer subtraction. It is recommended that
H A Dqe.txt5 in with the CPM binding later in this document.
17 - model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-platform-devices-ampere-smpro37 …| CPM (core) | 0 | 0 | Snoop-Logic | CPM # …
39 …| CPM (core) | 0 | 2 | Armv8 Core 1 | CPM # …
/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
H A Dpincfg.txt24 QE and two options for CPM.
H A Ducc.txt18 CPM UART driver, the port-number is required for the QE UART driver.
/openbmc/linux/arch/powerpc/
H A DKconfig.debug242 bool "Early serial debugging for Freescale CPM-based serial ports"
246 using a CPM-based serial port. This assumes that the bootwrapper
247 has run, and set up the CPM in a particular way.
352 hex "CPM UART early debug transmit descriptor address"
H A DKconfig1121 PPC4xx Clock Power Management (CPM) support (suspend/resume).
/openbmc/linux/arch/powerpc/platforms/8xx/
H A DKconfig4 select CPM
94 menu "MPC8xx CPM Options"
/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/
H A Di2c.txt3 The I2C controller is expressed as a bus under the CPM node.
/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8040-mcbin.dtsi65 /* CON15,16 - CPM lane 4 */
245 /* CPM Lane 5 - U29 */
H A Darmada-7040-db.dts146 * SPI on CPM and NAND have common pins on this board. We can
H A Darmada-cp11x.dtsi474 * this controller is only usable on the CPM
/openbmc/linux/drivers/pci/controller/
H A Dpcie-xilinx-cpm.c105 CPM, enumerator
635 .version = CPM,
H A DKconfig338 bool "Xilinx Versal CPM PCI controller"
343 Xilinx Versal CPM host bridge.
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A D8xxx_gpio.txt3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
/openbmc/linux/arch/powerpc/platforms/
H A DKconfig255 select CPM
276 config CPM config
/openbmc/u-boot/arch/arm/dts/
H A Drk3399-gru.dtsi744 * Since our pcie doesn't support ClockPM(CPM), we want
746 * de-assert it along and make ClockPM(CPM) work.
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru.dtsi765 * Since our pcie doesn't support ClockPM(CPM), we want
767 * de-assert it along and make ClockPM(CPM) work.
/openbmc/linux/drivers/usb/gadget/udc/
H A DKconfig316 tristate "Freescale QE/CPM USB Device Controller"
317 depends on FSL_SOC && (QUICC_ENGINE || CPM)
/openbmc/linux/drivers/tty/serial/
H A DKconfig764 tristate "CPM SCC/SMC serial port support"
772 bool "Support for console on CPM SCC/SMC serial port"
776 Say Y here if you wish to use a SCC or SMC CPM UART as the system
/openbmc/u-boot/doc/
H A DREADME.POST697 MPC8xx communication processor module (CPM) will be tested:
/openbmc/linux/drivers/spi/
H A DKconfig598 MPC83xx platform uses the controller in cpu mode or CPM/QE mode.
/openbmc/linux/Documentation/admin-guide/
H A Ddevices.txt2692 46 = /dev/ttyCPM0 PPC CPM (SCC or SMC) - port 0
2694 51 = /dev/ttyCPM5 PPC CPM (SCC or SMC) - port 5

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