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Searched refs:CP0_SRSConf4 (Results 1 – 7 of 7) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu.c242 env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4; in mips_cpu_reset_hold()
H A Dinternal.h78 int32_t CP0_SRSConf4; member
H A Dcpu.h728 int32_t CP0_SRSConf4; member
H A Dcpu-defs.c.inc313 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
/openbmc/qemu/target/mips/sysemu/
H A Dmachine.c280 VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU),
/openbmc/qemu/target/mips/tcg/sysemu/
H A Dcp0_helper.c1047 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask; in helper_mtc0_srsconf4()
/openbmc/qemu/target/mips/tcg/
H A Dtranslate.c5372 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); in gen_mfc0()
6854 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); in gen_dmfc0()