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Searched refs:CP0_SRSConf3 (Results 1 – 7 of 7) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu.c240 env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3; in mips_cpu_reset_hold()
H A Dinternal.h76 int32_t CP0_SRSConf3; member
H A Dcpu.h722 int32_t CP0_SRSConf3; member
H A Dcpu-defs.c.inc310 .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
/openbmc/qemu/target/mips/sysemu/
H A Dmachine.c279 VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU),
/openbmc/qemu/target/mips/tcg/sysemu/
H A Dcp0_helper.c1042 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask; in helper_mtc0_srsconf3()
/openbmc/qemu/target/mips/tcg/
H A Dtranslate.c5367 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); in gen_mfc0()
6849 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); in gen_dmfc0()