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Searched refs:CP0_EBaseWG_rw_bitmask (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu-defs.c.inc457 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
687 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
771 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
811 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
H A Dcpu.c245 env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask; in mips_cpu_reset_hold()
H A Dinternal.h81 target_ulong CP0_EBaseWG_rw_bitmask; member
H A Dcpu.h828 target_ulong CP0_EBaseWG_rw_bitmask; member
/openbmc/qemu/target/mips/tcg/sysemu/
H A Dcp0_helper.c1213 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask; in helper_mtc0_ebase()
1214 if (arg1 & env->CP0_EBaseWG_rw_bitmask) { in helper_mtc0_ebase()
1224 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask; in helper_mttc0_ebase()
1225 if (arg1 & env->CP0_EBaseWG_rw_bitmask) { in helper_mttc0_ebase()