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Searched refs:CP0_Config5_rw_bitmask (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu-defs.c.inc446 .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
488 .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
529 .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
761 .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
801 .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
912 .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
H A Dcpu.c211 env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask; in mips_cpu_reset_hold()
H A Dinternal.h42 int32_t CP0_Config5_rw_bitmask; member
H A Dcpu.h927 int32_t CP0_Config5_rw_bitmask; member
/openbmc/qemu/target/mips/tcg/sysemu/
H A Dcp0_helper.c1277 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) | in helper_mtc0_config5()
1278 (arg1 & env->CP0_Config5_rw_bitmask); in helper_mtc0_config5()