| /openbmc/linux/net/devlink/ |
| H A D | trap.c | 988 DEVLINK_TRAP(STP, CONTROL),
989 DEVLINK_TRAP(LACP, CONTROL),
990 DEVLINK_TRAP(LLDP, CONTROL),
991 DEVLINK_TRAP(IGMP_QUERY, CONTROL),
992 DEVLINK_TRAP(IGMP_V1_REPORT, CONTROL),
993 DEVLINK_TRAP(IGMP_V2_REPORT, CONTROL),
994 DEVLINK_TRAP(IGMP_V3_REPORT, CONTROL),
995 DEVLINK_TRAP(IGMP_V2_LEAVE, CONTROL),
996 DEVLINK_TRAP(MLD_QUERY, CONTROL),
997 DEVLINK_TRAP(MLD_V1_REPORT, CONTROL),
[all …]
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| /openbmc/qemu/include/hw/rtc/ |
| H A D | xlnx-zynqmp-rtc.h | 72 REG32(CONTROL, 0x40)
73 FIELD(CONTROL, BATTERY_DISABLE, 31, 1)
74 FIELD(CONTROL, OSC_CNTRL, 24, 4)
75 FIELD(CONTROL, SLVERR_ENABLE, 0, 1)
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| /openbmc/linux/drivers/parport/ |
| H A D | parport_gsc.c | 83 s->u.pc.ctr = parport_readb (CONTROL (p)); in parport_gsc_save_state()
88 parport_writeb (s->u.pc.ctr, CONTROL (p)); in parport_gsc_restore_state()
147 parport_writeb (w, CONTROL (pb)); in parport_SPP_supported()
154 r = parport_readb (CONTROL (pb)); in parport_SPP_supported()
157 parport_writeb (w, CONTROL (pb)); in parport_SPP_supported()
158 r = parport_readb (CONTROL (pb)); in parport_SPP_supported()
159 parport_writeb (0xc, CONTROL (pb)); in parport_SPP_supported()
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| H A D | parport_gsc.h | 47 #define CONTROL(p) ((p)->base + 0x2) macro
101 parport_writeb (ctr, CONTROL (p)); in __parport_gsc_frob_control()
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| H A D | parport_pc.c | 259 outb(c, CONTROL(p)); in parport_pc_restore_state()
1430 outb(w, CONTROL(pb)); in parport_SPP_supported()
1437 r = inb(CONTROL(pb)); in parport_SPP_supported()
1440 outb(w, CONTROL(pb)); in parport_SPP_supported()
1441 r = inb(CONTROL(pb)); in parport_SPP_supported()
1442 outb(0xc, CONTROL(pb)); in parport_SPP_supported()
1502 outb(r, CONTROL(pb)); in parport_ECR_present()
1504 outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */ in parport_ECR_present()
1506 r = inb(CONTROL(pb)); in parport_ECR_present()
1521 outb(0xc, CONTROL(pb)); in parport_ECR_present()
[all …]
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| /openbmc/qemu/hw/rtc/ |
| H A D | aspeed_rtc.c | 21 #define CONTROL (0x10 / 4) macro
78 if (rtc->reg[CONTROL] & RTC_ENABLED) { in aspeed_rtc_read()
82 case CONTROL: in aspeed_rtc_read()
106 if (!(rtc->reg[CONTROL] & RTC_UNLOCKED)) { in aspeed_rtc_write()
110 case CONTROL: in aspeed_rtc_write()
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| /openbmc/linux/drivers/clocksource/ |
| H A D | timer-digicolor.c | 48 #define CONTROL(t) ((t)*8) macro
72 writeb(CONTROL_DISABLE, dt->base + CONTROL(dt->timer_id)); in dc_timer_disable()
78 writeb(CONTROL_ENABLE | mode, dt->base + CONTROL(dt->timer_id)); in dc_timer_enable()
180 writeb(CONTROL_DISABLE, dc_timer_dev.base + CONTROL(TIMER_B)); in digicolor_timer_init()
182 writeb(CONTROL_ENABLE, dc_timer_dev.base + CONTROL(TIMER_B)); in digicolor_timer_init()
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| /openbmc/qemu/hw/timer/ |
| H A D | cmsdk-apb-dualtimer.c | 35 FIELD(CONTROL, ONESHOT, 0, 1)
36 FIELD(CONTROL, SIZE, 1, 1)
37 FIELD(CONTROL, PRESCALE, 2, 2)
38 FIELD(CONTROL, INTEN, 5, 1)
39 FIELD(CONTROL, MODE, 6, 1)
40 FIELD(CONTROL, ENABLE, 7, 1)
112 switch (FIELD_EX32(m->control, CONTROL, PRESCALE)) { in cmsdk_dualtimermod_divisor()
145 switch (FIELD_EX32(newctrl, CONTROL, PRESCALE)) { in cmsdk_dualtimermod_write_control()
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| /openbmc/linux/include/linux/ |
| H A D | parport_pc.h | 15 #define CONTROL(p) ((p)->base + 0x2) macro
89 unsigned char dcr = inb (CONTROL (p)); in dump_parport_state()
103 dcr = i ? priv->ctr : inb (CONTROL (p)); in dump_parport_state()
144 outb (ctr, CONTROL (p)); in __parport_pc_frob_control()
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| /openbmc/linux/sound/pci/ |
| H A D | ens1370.c | 679 inl(ES_REG(ensoniq, CONTROL)); in snd_es1371_codec_read()
838 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_ensoniq_trigger()
873 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_ensoniq_playback1_prepare()
892 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_ensoniq_playback1_prepare()
914 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_ensoniq_playback2_prepare()
932 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_ensoniq_playback2_prepare()
954 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_ensoniq_capture_prepare()
970 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); in snd_ensoniq_capture_prepare()
984 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) { in snd_ensoniq_playback1_pointer()
1001 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) { in snd_ensoniq_playback2_pointer()
[all …]
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| /openbmc/qemu/hw/ssi/ |
| H A D | ibex_spi_host.c | 48 REG32(CONTROL, 0x10)
49 FIELD(CONTROL, RX_WATERMARK, 0, 8)
50 FIELD(CONTROL, TX_WATERMARK, 1, 8)
51 FIELD(CONTROL, OUTPUT_EN, 29, 1)
52 FIELD(CONTROL, SW_RST, 30, 1)
53 FIELD(CONTROL, SPIEN, 31, 1)
416 CONTROL, SPIEN))) { in ibex_spi_host_write()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| H A D | dcn31_optc.c | 106 REG_UPDATE(CONTROL, in optc31_enable_crtc()
132 REG_UPDATE(CONTROL, in optc31_disable_crtc()
152 REG_UPDATE(CONTROL, in optc31_immediate_disable_crtc()
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| /openbmc/openbmc/poky/meta/files/common-licenses/ |
| H A D | Widget-Workshop | 13 CONTROL EQUIPMENT IN HAZARDOUS ENVIRONMENTS REQUIRING FAIL-SAFE PERFORMANCE,
15 COMMUNICATION SYSTEMS, AIR TRAFFIC CONTROL, DIRECT LIFE SUPPORT MACHINES,
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| /openbmc/linux/drivers/watchdog/ |
| H A D | machzwd.c | 52 #define CONTROL 0x10 /* 16 */ macro
155 return zf_readw(CONTROL); in zf_get_control()
160 zf_writew(CONTROL, new); in zf_set_control()
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| /openbmc/linux/drivers/bluetooth/ |
| H A D | bt3c_cs.c | 113 #define CONTROL 4 macro
349 iir = inb(iobase + CONTROL); in bt3c_interrupt()
370 outb(iir, iobase + CONTROL); in bt3c_interrupt()
524 outb(inb(iobase + CONTROL) | 0x40, iobase + CONTROL); in bt3c_load_firmware()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/ |
| H A D | dcn314_optc.c | 115 REG_UPDATE(CONTROL, in optc314_enable_crtc()
142 REG_UPDATE(CONTROL, in optc314_disable_crtc()
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| /openbmc/linux/Documentation/devicetree/bindings/timer/ |
| H A D | marvell,orion-timer.txt | 5 - reg: base address of the timer register starting with TIMERS CONTROL register
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| /openbmc/linux/Documentation/leds/ |
| H A D | leds-lm3556.rst | 23 CONTROL REGISTER(0x09).Flash mode is activated by the ENABLE REGISTER(0x0A),
50 In Torch Mode, the current source(LED) is programmed via the CURRENT CONTROL
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_optc.c | 124 REG_UPDATE(CONTROL, in optc32_enable_crtc()
161 REG_UPDATE(CONTROL, in optc32_disable_crtc()
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| /openbmc/linux/drivers/hwmon/ |
| H A D | adt7475.c | 29 #define CONTROL 3 macro
789 data->pwm[CONTROL][sattr->index] = in pwm_store()
796 if (((data->pwm[CONTROL][sattr->index] >> 5) & 7) != 7) { in pwm_store()
907 data->pwm[CONTROL][index] &= ~0xE0; in hw_set_pwm()
908 data->pwm[CONTROL][index] |= (val & 7) << 5; in hw_set_pwm()
911 data->pwm[CONTROL][index]); in hw_set_pwm()
1843 data->pwm[CONTROL][index] = adt7475_read(PWM_CONFIG_REG(index)); in adt7475_read_pwm()
1849 v = (data->pwm[CONTROL][index] >> 5) & 7; in adt7475_read_pwm()
1862 data->pwm[CONTROL][index] &= ~0xE0; in adt7475_read_pwm()
1863 data->pwm[CONTROL][index] |= (7 << 5); in adt7475_read_pwm()
[all …]
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| /openbmc/linux/drivers/media/usb/uvc/ |
| H A D | uvc_ctrl.c | 953 uvc_dbg(chain->dev, CONTROL, "Control 0x%08x not found\n", in uvc_find_control()
2152 uvc_dbg(dev, CONTROL, in uvc_ctrl_fill_xu_info()
2165 uvc_dbg(dev, CONTROL, in uvc_ctrl_fill_xu_info()
2173 uvc_dbg(dev, CONTROL, in uvc_ctrl_fill_xu_info()
2203 uvc_dbg(dev, CONTROL, in uvc_ctrl_init_xu_ctrl()
2234 uvc_dbg(chain->dev, CONTROL, "Extension unit %u not found\n", in uvc_xu_ctrl_query()
2250 uvc_dbg(chain->dev, CONTROL, "Control %pUl/%u not found\n", in uvc_xu_ctrl_query()
2399 uvc_dbg(dev, CONTROL, "Added control %pUl/%u to device %s entity %u\n", in uvc_ctrl_add_info()
2469 uvc_dbg(chain->dev, CONTROL, "Adding mapping '%s' to control %pUl/%u\n", in __uvc_ctrl_add_mapping()
2494 uvc_dbg(dev, CONTROL, in uvc_ctrl_add_mapping()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_opp.h | 78 SRI(CONTROL, FMT_MEMORY, id)
82 SRI(CONTROL, FMT_MEMORY, id)
295 uint32_t CONTROL; member
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| /openbmc/linux/drivers/scsi/ |
| H A D | aha1542.h | 29 #define CONTROL(base) STATUS(base) macro
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| /openbmc/linux/drivers/net/ethernet/smsc/ |
| H A D | smc9194.c | 338 outw( inw( ioaddr + CONTROL ) | CTL_AUTO_RELEASE , ioaddr + CONTROL ); in smc_reset()
398 outw( inw( ioaddr + CONTROL ), CTL_POWERDOWN, ioaddr + CONTROL ); in smc_shutdown()
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| H A D | smc9194.h | 104 #define CONTROL 12 macro
|