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Searched refs:CONFIG_SYS_SDRAM_BASE (Results 1 – 25 of 602) sorted by relevance

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/openbmc/u-boot/include/configs/
H A Dexynos5-common.h53 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
54 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
55 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
59 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
61 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
63 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
65 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
67 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
69 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
71 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
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H A Dexynos7420-common.h47 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
49 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
51 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
53 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
55 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
57 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
59 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
61 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
63 #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
H A Dsmdkv310.h23 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
47 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
48 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
49 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
53 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
55 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
57 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
59 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
H A Dsmdkc100.h30 #define CONFIG_SYS_SDRAM_BASE 0x30000000 macro
115 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
116 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5e00000)
117 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
120 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
138 #define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE
H A Dboston.h27 # define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 macro
29 # define CONFIG_SYS_SDRAM_BASE 0x80000000 macro
36 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000)
38 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0)
39 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x10000000)
H A Dat91rm9200ek.h57 #define CONFIG_SYS_SDRAM_BASE 0x20000000 macro
60 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
85 #define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
86 #define CONFIG_SYS_SDRAM1 (CONFIG_SYS_SDRAM_BASE+0x80)
158 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M
171 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
H A Dtrats.h25 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
26 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
30 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
31 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
32 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
159 #define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100
H A Dorigen.h20 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
21 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
25 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
26 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
27 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
H A Dmalta.h36 # define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 macro
38 # define CONFIG_SYS_SDRAM_BASE 0x80000000 macro
44 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x01000000)
45 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000)
46 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x00800000)
H A Dodroid.h24 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
26 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
32 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
33 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
34 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
H A Dr2dplus.h15 #define CONFIG_SYS_SDRAM_BASE 0x8C000000 macro
20 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
23 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
78 #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
79 #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
H A Ds5pc210_universal.h20 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
21 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
40 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
41 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
42 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
H A Ds5p_goni.h27 #define CONFIG_SYS_SDRAM_BASE 0x30000000 macro
152 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
153 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
154 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000000)
157 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */
H A Dtrats2.h24 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
25 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
28 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
29 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
30 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
H A Dr7780mp.h23 #define CONFIG_SYS_SDRAM_BASE (0x08000000) macro
28 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
49 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
91 #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
92 #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
H A Dstmark2.h95 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
115 #define CONFIG_SYS_SDRAM_BASE 0x40000000 macro
118 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
144 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
168 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
H A Dmeesc.h61 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM macro
64 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000)
65 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000)
66 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000)
H A DM5235EVB.h92 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000)
118 #define CONFIG_SYS_SDRAM_BASE 0x00000000 macro
121 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
136 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
183 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
H A Dwork_92105.h32 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE macro
34 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K)
37 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
39 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \
H A Ddevkit3250.h27 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE macro
29 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K)
32 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
34 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
/openbmc/u-boot/board/freescale/m5275evb/
H A Dm5275evb.c36 out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE); in dram_init()
50 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
56 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
60 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
67 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
72 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
73 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
77 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; in dram_init()
/openbmc/u-boot/arch/arm/mach-at91/arm926ejs/
H A Dlowlevel_init.S204 .word CONFIG_SYS_SDRAM_BASE
208 .word CONFIG_SYS_SDRAM_BASE
210 .word CONFIG_SYS_SDRAM_BASE
212 .word CONFIG_SYS_SDRAM_BASE
214 .word CONFIG_SYS_SDRAM_BASE
216 .word CONFIG_SYS_SDRAM_BASE
218 .word CONFIG_SYS_SDRAM_BASE
220 .word CONFIG_SYS_SDRAM_BASE
222 .word CONFIG_SYS_SDRAM_BASE
226 .word CONFIG_SYS_SDRAM_BASE
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/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_helpers.c32 writel(0, CONFIG_SYS_SDRAM_BASE); in mctl_mem_matches()
33 writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset); in mctl_mem_matches()
36 return readl(CONFIG_SYS_SDRAM_BASE) == in mctl_mem_matches()
37 readl((ulong)CONFIG_SYS_SDRAM_BASE + offset); in mctl_mem_matches()
/openbmc/u-boot/board/ti/ks2_evm/
H A Dboard.c44 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, in dram_init()
81 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; in board_init()
131 start[0] -= CONFIG_SYS_SDRAM_BASE; in ft_board_setup()
185 initrd_start -= CONFIG_SYS_SDRAM_BASE; in ft_board_setup_ex()
189 initrd_end -= CONFIG_SYS_SDRAM_BASE; in ft_board_setup_ex()
232 *reserve_start -= CONFIG_SYS_SDRAM_BASE; in ft_board_setup_ex()
/openbmc/u-boot/board/astro/mcf5373l/
H A Dmcf5373l.c41 __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018, in dram_init()
43 __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000, in dram_init()
71 writel(0, CONFIG_SYS_SDRAM_BASE); in dram_init()
81 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, in dram_init()
82 0x80000000 - CONFIG_SYS_SDRAM_BASE); in dram_init()

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