1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2e21185baSChander Kashyap /* 3e21185baSChander Kashyap * Copyright (C) 2011 Samsung Electronics 4e21185baSChander Kashyap * 5393cb361SChander Kashyap * Configuration settings for the SAMSUNG SMDKV310 (EXYNOS4210) board. 6e21185baSChander Kashyap */ 7e21185baSChander Kashyap 8e21185baSChander Kashyap #ifndef __CONFIG_H 9e21185baSChander Kashyap #define __CONFIG_H 10e21185baSChander Kashyap 111d551100SSimon Glass #include "exynos4-common.h" 121d551100SSimon Glass 131d551100SSimon Glass #undef CONFIG_BOARD_COMMON 14e30824f4SMarek Vasut #undef CONFIG_USB_GADGET_DWC2_OTG_PHY 151d551100SSimon Glass #undef CONFIG_REVISION_TAG 161d551100SSimon Glass 17e21185baSChander Kashyap /* High Level Configuration Options */ 18393cb361SChander Kashyap #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ 19e21185baSChander Kashyap 20b3c5a49bSChander Kashyap /* Mach Type */ 21b3c5a49bSChander Kashyap #define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310 22b3c5a49bSChander Kashyap 23e21185baSChander Kashyap #define CONFIG_SYS_SDRAM_BASE 0x40000000 24e21185baSChander Kashyap 25e21185baSChander Kashyap /* Handling Sleep Mode*/ 26e21185baSChander Kashyap #define S5P_CHECK_SLEEP 0x00000BAD 27e21185baSChander Kashyap #define S5P_CHECK_DIDLE 0xBAD00000 28643be9c0SRajeshwari Shinde #define S5P_CHECK_LPA 0xABAD0000 29e21185baSChander Kashyap 30e21185baSChander Kashyap /* select serial console configuration */ 31393cb361SChander Kashyap #define EXYNOS4_DEFAULT_UART_OFFSET 0x010000 32e21185baSChander Kashyap 33e21185baSChander Kashyap /* allow to overwrite serial and ethaddr */ 34e21185baSChander Kashyap #define CONFIG_ENV_OVERWRITE 35e21185baSChander Kashyap 365187d8ddSChander Kashyap /* MMC SPL */ 37643be9c0SRajeshwari Shinde #define CONFIG_SKIP_LOWLEVEL_INIT 389b3ab1c9SChander Kashyap #define COPY_BL2_FNPTR_ADDR 0x00002488 39e21185baSChander Kashyap 408a00061eSInderpal Singh #define CONFIG_SPL_TEXT_BASE 0x02021410 418a00061eSInderpal Singh 42e21185baSChander Kashyap #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" 43e21185baSChander Kashyap 44e21185baSChander Kashyap /* Miscellaneous configurable options */ 45e21185baSChander Kashyap #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" 46e21185baSChander Kashyap /* memtest works on */ 47e21185baSChander Kashyap #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 48e21185baSChander Kashyap #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) 49e21185baSChander Kashyap #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) 50e21185baSChander Kashyap 51e21185baSChander Kashyap /* SMDKV310 has 4 bank of DRAM */ 52e21185baSChander Kashyap #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ 53e21185baSChander Kashyap #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 54e21185baSChander Kashyap #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE 55e21185baSChander Kashyap #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) 56e21185baSChander Kashyap #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE 57e21185baSChander Kashyap #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) 58e21185baSChander Kashyap #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE 59e21185baSChander Kashyap #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) 60e21185baSChander Kashyap #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE 61e21185baSChander Kashyap 62e21185baSChander Kashyap /* FLASH and environment organization */ 63e21185baSChander Kashyap 64e21185baSChander Kashyap #define CONFIG_CLK_1000_400_200 65e21185baSChander Kashyap 66e21185baSChander Kashyap /* MIU (Memory Interleaving Unit) */ 67e21185baSChander Kashyap #define CONFIG_MIU_2BIT_INTERLEAVED 68e21185baSChander Kashyap 69e21185baSChander Kashyap #define CONFIG_SYS_MMC_ENV_DEV 0 70e21185baSChander Kashyap #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ 71e21185baSChander Kashyap #define RESERVE_BLOCK_SIZE (512) 72e21185baSChander Kashyap #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ 73e21185baSChander Kashyap #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) 74e21185baSChander Kashyap 75643be9c0SRajeshwari Shinde #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) 76643be9c0SRajeshwari Shinde 77643be9c0SRajeshwari Shinde #define CONFIG_SYS_INIT_SP_ADDR 0x02040000 78e21185baSChander Kashyap 79a187559eSBin Meng /* U-Boot copy size from boot Media to DRAM.*/ 80e21185baSChander Kashyap #define COPY_BL2_SIZE 0x80000 81e21185baSChander Kashyap #define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512) 82e21185baSChander Kashyap #define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512) 83e21185baSChander Kashyap 84e21185baSChander Kashyap /* Ethernet Controllor Driver */ 85e21185baSChander Kashyap #ifdef CONFIG_CMD_NET 86e21185baSChander Kashyap #define CONFIG_ENV_SROM_BANK 1 87e21185baSChander Kashyap #endif /*CONFIG_CMD_NET*/ 8807407d97SThomas Abraham 89e21185baSChander Kashyap #endif /* __CONFIG_H */ 90