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Searched refs:CONFIG_SYS_DDR_RAW_TIMING (Results 1 – 25 of 25) sorted by relevance

/openbmc/u-boot/board/freescale/ls1043ardb/
H A Dddr.c103 #ifdef CONFIG_SYS_DDR_RAW_TIMING
213 #ifdef CONFIG_SYS_DDR_RAW_TIMING in fsl_initdram()
225 #ifdef CONFIG_SYS_DDR_RAW_TIMING in fsl_initdram()
H A Dddr.h47 #ifndef CONFIG_SYS_DDR_RAW_TIMING
/openbmc/u-boot/board/freescale/t102xrdb/
H A Dddr.c148 #ifdef CONFIG_SYS_DDR_RAW_TIMING
236 #ifndef CONFIG_SYS_DDR_RAW_TIMING in dram_init()
/openbmc/u-boot/include/configs/
H A Dls2080a_common.h38 #define CONFIG_SYS_DDR_RAW_TIMING macro
H A DP1023RDB.h65 #define CONFIG_SYS_DDR_RAW_TIMING macro
H A DBSC9131RDB.h66 #undef CONFIG_SYS_DDR_RAW_TIMING
H A Dls1043ardb.h23 #define CONFIG_SYS_DDR_RAW_TIMING macro
H A DC29XPCIE.h119 #define CONFIG_SYS_DDR_RAW_TIMING macro
H A DUCP1020.h132 #define CONFIG_SYS_DDR_RAW_TIMING macro
H A Dls1021aqds.h93 #define CONFIG_SYS_DDR_RAW_TIMING macro
H A DB4860QDS.h192 #define CONFIG_SYS_DDR_RAW_TIMING macro
H A DP1010RDB.h208 #define CONFIG_SYS_DDR_RAW_TIMING macro
H A Dp1_p2_rdb_pc.h265 #define CONFIG_SYS_DDR_RAW_TIMING macro
H A DT102xRDB.h241 #define CONFIG_SYS_DDR_RAW_TIMING macro
/openbmc/u-boot/board/Arcturus/ucp1020/
H A Dddr.c19 #ifdef CONFIG_SYS_DDR_RAW_TIMING
/openbmc/u-boot/board/freescale/bsc9131rdb/
H A Dddr.c15 #ifndef CONFIG_SYS_DDR_RAW_TIMING
/openbmc/u-boot/board/freescale/ls2080a/
H A Dddr.c114 #ifdef CONFIG_SYS_DDR_RAW_TIMING
/openbmc/u-boot/board/freescale/ls1021aqds/
H A Dddr.c108 #ifdef CONFIG_SYS_DDR_RAW_TIMING
/openbmc/u-boot/board/freescale/bsc9132qds/
H A Dddr.c15 #ifndef CONFIG_SYS_DDR_RAW_TIMING
/openbmc/u-boot/board/freescale/p1010rdb/
H A Dddr.c17 #ifndef CONFIG_SYS_DDR_RAW_TIMING
/openbmc/u-boot/board/freescale/p1_p2_rdb_pc/
H A Dddr.c15 #ifdef CONFIG_SYS_DDR_RAW_TIMING
/openbmc/u-boot/drivers/ddr/fsl/
H A Dmain.c460 #ifdef CONFIG_SYS_DDR_RAW_TIMING in fsl_ddr_compute()
497 #elif defined(CONFIG_SYS_DDR_RAW_TIMING) in fsl_ddr_compute()
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dcpu.c444 defined(CONFIG_SYS_DDR_RAW_TIMING) in dram_init()
/openbmc/u-boot/scripts/
H A Dconfig_whitelist.txt2372 CONFIG_SYS_DDR_RAW_TIMING
/openbmc/u-boot/
H A DREADME3194 - CONFIG_SYS_DDR_RAW_TIMING