Searched refs:CLK_DIVIDER (Results 1 – 9 of 9) sorted by relevance
17 #define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) macro
28 #define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) macro
392 src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ); in clock_enable_coresight()
90 CLK_DIVIDER, /* Rx = DPLL, Tx = divider (fullduplex with */ enumerator
38 # define CLK_DIVIDER(x) ((x) << 8) macro
554 value |= CLK_DIVIDER(dividers.post_div); in trinity_set_divider_value()
158 CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); in t114_init_clocks()
203 CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); in tegra124_init_clocks()
846 case CLK_DIVIDER: in init_channel()