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Searched refs:CAR (Results 1 – 15 of 15) sorted by relevance

/openbmc/u-boot/board/coreboot/coreboot/
H A DKconfig23 hex "Board specific Cache-As-RAM (CAR) address"
26 This option specifies the board specific Cache-As-RAM (CAR) address.
29 hex "Board specific Cache-As-RAM (CAR) size"
32 This option specifies the board specific Cache-As-RAM (CAR) size.
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dnvidia,tegra20-car.txt6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
11 - reg : Should contain CAR registers location and length
15 In clock consumers, this cell represents the clock ID exposed by the CAR.
17 The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
18 registers. These IDs often match those in the CAR's RST_DEVICES registers,
25 The balance of the clocks controlled by the CAR are assigned IDs of 96 and
/openbmc/u-boot/drivers/clk/tegra/
H A DKconfig2 bool "Enable Tegra CAR-based clock driver"
6 register access to the Tegra CAR (Clock And Reset controller).
/openbmc/u-boot/arch/x86/cpu/tangier/
H A DKconfig27 Space in bytes in eSRAM used as Cache-As-RAM (CAR).
/openbmc/linux/sound/arm/
H A Dpxa2xx-ac97-regs.h70 #define CAR (0x0020) /* CODEC Access Register */ macro
/openbmc/u-boot/doc/device-tree-bindings/i2c/
H A Dtegra20-i2c.txt7 CAR node and the clock number as a parameter:
/openbmc/u-boot/drivers/reset/
H A DKconfig39 bool "Enable Tegra CAR-based reset driver"
43 direct register access to the Tegra CAR (Clock And Reset controller).
/openbmc/u-boot/arch/x86/
H A DKconfig379 CAR is disabled.
458 start address of the cache-as-RAM (CAR) area and the address varies
459 depending on the CPU. Once CAR is set up, read/write memory becomes
469 sets the size of the cache-as-RAM (CAR) area. Note that much of the
470 CAR space is required by the MRC. The CAR space available to U-Boot
478 This is the amount of CAR (Cache as RAM) reserved for use by the
/openbmc/u-boot/arch/x86/cpu/quark/
H A DKconfig130 Space in bytes in eSRAM used as Cache-As-ARM (CAR).
/openbmc/u-boot/drivers/misc/
H A DKconfig212 bool "Enable support for the Tegra CAR driver"
215 The Tegra CAR (Clock and Reset Controller) is a HW module that
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h412 #define CAR 0x40500020 /* CODEC Access Register */ macro
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124.dtsi918 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
/openbmc/u-boot/
H A DMAINTAINERS223 ARM RENESAS RMOBILE/R-CAR
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra210.dtsi1319 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
/openbmc/linux/
H A DMAINTAINERS9320 HID VRC-2 CAR CONTROLLER DRIVER
16465 PCI DRIVER FOR RENESAS R-CAR
18285 RENESAS R-CAR GEN3 & RZ/N1 NAND CONTROLLER DRIVER
18293 RENESAS R-CAR GYROADC DRIVER
18300 RENESAS R-CAR I2C DRIVERS
18309 RENESAS R-CAR SATA DRIVER
18317 RENESAS R-CAR THERMAL DRIVERS