1 menu "x86 architecture" 2 depends on X86 3 4 config SYS_ARCH 5 default "x86" 6 7 choice 8 prompt "Run U-Boot in 32/64-bit mode" 9 default X86_RUN_32BIT 10 help 11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode 12 even on 64-bit machines. In this case SPL is not used, and U-Boot 13 runs directly from the reset vector (via 16-bit start-up). 14 15 Alternatively it can be run as a 64-bit binary, thus requiring a 16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit 17 start-up) then jumps to U-Boot in 64-bit mode. 18 19 For now, 32-bit mode is recommended, as 64-bit is still 20 experimental and is missing a lot of features. 21 22 config X86_RUN_32BIT 23 bool "32-bit" 24 help 25 Build U-Boot as a 32-bit binary with no SPL. This is the currently 26 supported normal setup. U-Boot will stay in 32-bit mode even on 27 64-bit machines. When booting a 64-bit kernel, U-Boot will switch 28 to 64-bit just before starting the kernel. Only the bottom 4GB of 29 memory can be accessed through normal means, although 30 arch_phys_memset() can be used for basic access to other memory. 31 32 config X86_RUN_64BIT 33 bool "64-bit" 34 select X86_64 35 select SUPPORT_SPL 36 select SPL 37 select SPL_SEPARATE_BSS 38 help 39 Build U-Boot as a 64-bit binary with a 32-bit SPL. This is 40 experimental and many features are missing. U-Boot SPL starts up, 41 runs through the 16-bit and 32-bit init, then switches to 64-bit 42 mode and jumps to U-Boot proper. 43 44 endchoice 45 46 config X86_64 47 bool 48 49 config SPL_X86_64 50 bool 51 depends on SPL 52 53 choice 54 prompt "Mainboard vendor" 55 default VENDOR_EMULATION 56 57 config VENDOR_ADVANTECH 58 bool "advantech" 59 60 config VENDOR_CONGATEC 61 bool "congatec" 62 63 config VENDOR_COREBOOT 64 bool "coreboot" 65 66 config VENDOR_DFI 67 bool "dfi" 68 69 config VENDOR_EFI 70 bool "efi" 71 72 config VENDOR_EMULATION 73 bool "emulation" 74 75 config VENDOR_GOOGLE 76 bool "Google" 77 78 config VENDOR_INTEL 79 bool "Intel" 80 81 endchoice 82 83 # subarchitectures-specific options below 84 config INTEL_MID 85 bool "Intel MID platform support" 86 select REGMAP 87 select SYSCON 88 help 89 Select to build a U-Boot capable of supporting Intel MID 90 (Mobile Internet Device) platform systems which do not have 91 the PCI legacy interfaces. 92 93 If you are building for a PC class system say N here. 94 95 Intel MID platforms are based on an Intel processor and 96 chipset which consume less power than most of the x86 97 derivatives. 98 99 # board-specific options below 100 source "board/advantech/Kconfig" 101 source "board/congatec/Kconfig" 102 source "board/coreboot/Kconfig" 103 source "board/dfi/Kconfig" 104 source "board/efi/Kconfig" 105 source "board/emulation/Kconfig" 106 source "board/google/Kconfig" 107 source "board/intel/Kconfig" 108 109 # platform-specific options below 110 source "arch/x86/cpu/baytrail/Kconfig" 111 source "arch/x86/cpu/braswell/Kconfig" 112 source "arch/x86/cpu/broadwell/Kconfig" 113 source "arch/x86/cpu/coreboot/Kconfig" 114 source "arch/x86/cpu/ivybridge/Kconfig" 115 source "arch/x86/cpu/efi/Kconfig" 116 source "arch/x86/cpu/qemu/Kconfig" 117 source "arch/x86/cpu/quark/Kconfig" 118 source "arch/x86/cpu/queensbay/Kconfig" 119 source "arch/x86/cpu/tangier/Kconfig" 120 121 # architecture-specific options below 122 123 config AHCI 124 default y 125 126 config SYS_MALLOC_F_LEN 127 default 0x800 128 129 config RAMBASE 130 hex 131 default 0x100000 132 133 config XIP_ROM_SIZE 134 hex 135 depends on X86_RESET_VECTOR 136 default ROM_SIZE 137 138 config CPU_ADDR_BITS 139 int 140 default 36 141 142 config HPET_ADDRESS 143 hex 144 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE 145 146 config SMM_TSEG 147 bool 148 default n 149 150 config SMM_TSEG_SIZE 151 hex 152 153 config X86_RESET_VECTOR 154 bool 155 default n 156 select BINMAN 157 158 # The following options control where the 16-bit and 32-bit init lies 159 # If SPL is enabled then it normally holds this init code, and U-Boot proper 160 # is normally a 64-bit build. 161 # 162 # The 16-bit init refers to the reset vector and the small amount of code to 163 # get the processor into 32-bit mode. It may be in SPL or in U-Boot proper, 164 # or missing altogether if U-Boot is started from EFI or coreboot. 165 # 166 # The 32-bit init refers to processor init, running binary blobs including 167 # FSP, setting up interrupts and anything else that needs to be done in 168 # 32-bit code. It is normally in the same place as 16-bit init if that is 169 # enabled (i.e. they are both in SPL, or both in U-Boot proper). 170 config X86_16BIT_INIT 171 bool 172 depends on X86_RESET_VECTOR 173 default y if X86_RESET_VECTOR && !SPL 174 help 175 This is enabled when 16-bit init is in U-Boot proper 176 177 config SPL_X86_16BIT_INIT 178 bool 179 depends on X86_RESET_VECTOR 180 default y if X86_RESET_VECTOR && SPL 181 help 182 This is enabled when 16-bit init is in SPL 183 184 config X86_32BIT_INIT 185 bool 186 depends on X86_RESET_VECTOR 187 default y if X86_RESET_VECTOR && !SPL 188 help 189 This is enabled when 32-bit init is in U-Boot proper 190 191 config SPL_X86_32BIT_INIT 192 bool 193 depends on X86_RESET_VECTOR 194 default y if X86_RESET_VECTOR && SPL 195 help 196 This is enabled when 32-bit init is in SPL 197 198 config RESET_SEG_START 199 hex 200 depends on X86_RESET_VECTOR 201 default 0xffff0000 202 203 config RESET_SEG_SIZE 204 hex 205 depends on X86_RESET_VECTOR 206 default 0x10000 207 208 config RESET_VEC_LOC 209 hex 210 depends on X86_RESET_VECTOR 211 default 0xfffffff0 212 213 config SYS_X86_START16 214 hex 215 depends on X86_RESET_VECTOR 216 default 0xfffff800 217 218 config X86_LOAD_FROM_32_BIT 219 bool "Boot from a 32-bit program" 220 help 221 Define this to boot U-Boot from a 32-bit program which sets 222 the GDT differently. This can be used to boot directly from 223 any stage of coreboot, for example, bypassing the normal 224 payload-loading feature. 225 226 config BOARD_ROMSIZE_KB_512 227 bool 228 config BOARD_ROMSIZE_KB_1024 229 bool 230 config BOARD_ROMSIZE_KB_2048 231 bool 232 config BOARD_ROMSIZE_KB_4096 233 bool 234 config BOARD_ROMSIZE_KB_8192 235 bool 236 config BOARD_ROMSIZE_KB_16384 237 bool 238 239 choice 240 prompt "ROM chip size" 241 depends on X86_RESET_VECTOR 242 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 243 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 244 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 245 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 246 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 247 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 248 help 249 Select the size of the ROM chip you intend to flash U-Boot on. 250 251 The build system will take care of creating a u-boot.rom file 252 of the matching size. 253 254 config UBOOT_ROMSIZE_KB_512 255 bool "512 KB" 256 help 257 Choose this option if you have a 512 KB ROM chip. 258 259 config UBOOT_ROMSIZE_KB_1024 260 bool "1024 KB (1 MB)" 261 help 262 Choose this option if you have a 1024 KB (1 MB) ROM chip. 263 264 config UBOOT_ROMSIZE_KB_2048 265 bool "2048 KB (2 MB)" 266 help 267 Choose this option if you have a 2048 KB (2 MB) ROM chip. 268 269 config UBOOT_ROMSIZE_KB_4096 270 bool "4096 KB (4 MB)" 271 help 272 Choose this option if you have a 4096 KB (4 MB) ROM chip. 273 274 config UBOOT_ROMSIZE_KB_8192 275 bool "8192 KB (8 MB)" 276 help 277 Choose this option if you have a 8192 KB (8 MB) ROM chip. 278 279 config UBOOT_ROMSIZE_KB_16384 280 bool "16384 KB (16 MB)" 281 help 282 Choose this option if you have a 16384 KB (16 MB) ROM chip. 283 284 endchoice 285 286 # Map the config names to an integer (KB). 287 config UBOOT_ROMSIZE_KB 288 int 289 default 512 if UBOOT_ROMSIZE_KB_512 290 default 1024 if UBOOT_ROMSIZE_KB_1024 291 default 2048 if UBOOT_ROMSIZE_KB_2048 292 default 4096 if UBOOT_ROMSIZE_KB_4096 293 default 8192 if UBOOT_ROMSIZE_KB_8192 294 default 16384 if UBOOT_ROMSIZE_KB_16384 295 296 # Map the config names to a hex value (bytes). 297 config ROM_SIZE 298 hex 299 default 0x80000 if UBOOT_ROMSIZE_KB_512 300 default 0x100000 if UBOOT_ROMSIZE_KB_1024 301 default 0x200000 if UBOOT_ROMSIZE_KB_2048 302 default 0x400000 if UBOOT_ROMSIZE_KB_4096 303 default 0x800000 if UBOOT_ROMSIZE_KB_8192 304 default 0xc00000 if UBOOT_ROMSIZE_KB_12288 305 default 0x1000000 if UBOOT_ROMSIZE_KB_16384 306 307 config HAVE_INTEL_ME 308 bool "Platform requires Intel Management Engine" 309 help 310 Newer higher-end devices have an Intel Management Engine (ME) 311 which is a very large binary blob (typically 1.5MB) which is 312 required for the platform to work. This enforces a particular 313 SPI flash format. You will need to supply the me.bin file in 314 your board directory. 315 316 config X86_RAMTEST 317 bool "Perform a simple RAM test after SDRAM initialisation" 318 help 319 If there is something wrong with SDRAM then the platform will 320 often crash within U-Boot or the kernel. This option enables a 321 very simple RAM test that quickly checks whether the SDRAM seems 322 to work correctly. It is not exhaustive but can save time by 323 detecting obvious failures. 324 325 config FLASH_DESCRIPTOR_FILE 326 string "Flash descriptor binary filename" 327 depends on HAVE_INTEL_ME 328 default "descriptor.bin" 329 help 330 The filename of the file to use as flash descriptor in the 331 board directory. 332 333 config INTEL_ME_FILE 334 string "Intel Management Engine binary filename" 335 depends on HAVE_INTEL_ME 336 default "me.bin" 337 help 338 The filename of the file to use as Intel Management Engine in the 339 board directory. 340 341 config HAVE_FSP 342 bool "Add an Firmware Support Package binary" 343 depends on !EFI 344 help 345 Select this option to add an Firmware Support Package binary to 346 the resulting U-Boot image. It is a binary blob which U-Boot uses 347 to set up SDRAM and other chipset specific initialization. 348 349 Note: Without this binary U-Boot will not be able to set up its 350 SDRAM so will not boot. 351 352 config FSP_FILE 353 string "Firmware Support Package binary filename" 354 depends on HAVE_FSP 355 default "fsp.bin" 356 help 357 The filename of the file to use as Firmware Support Package binary 358 in the board directory. 359 360 config FSP_ADDR 361 hex "Firmware Support Package binary location" 362 depends on HAVE_FSP 363 default 0xfffc0000 364 help 365 FSP is not Position Independent Code (PIC) and the whole FSP has to 366 be rebased if it is placed at a location which is different from the 367 perferred base address specified during the FSP build. Use Intel's 368 Binary Configuration Tool (BCT) to do the rebase. 369 370 The default base address of 0xfffc0000 indicates that the binary must 371 be located at offset 0xc0000 from the beginning of a 1MB flash device. 372 373 config FSP_TEMP_RAM_ADDR 374 hex 375 depends on HAVE_FSP 376 default 0x2000000 377 help 378 Stack top address which is used in fsp_init() after DRAM is ready and 379 CAR is disabled. 380 381 config FSP_SYS_MALLOC_F_LEN 382 hex 383 depends on HAVE_FSP 384 default 0x100000 385 help 386 Additional size of malloc() pool before relocation. 387 388 config FSP_USE_UPD 389 bool 390 depends on HAVE_FSP 391 default y 392 help 393 Most FSPs use UPD data region for some FSP customization. But there 394 are still some FSPs that might not even have UPD. For such FSPs, 395 override this to n in their platform Kconfig files. 396 397 config FSP_BROKEN_HOB 398 bool 399 depends on HAVE_FSP 400 help 401 Indicate some buggy FSPs that does not report memory used by FSP 402 itself as reserved in the resource descriptor HOB. Select this to 403 tell U-Boot to do some additional work to ensure U-Boot relocation 404 do not overwrite the important boot service data which is used by 405 FSP, otherwise the subsequent call to fsp_notify() will fail. 406 407 config ENABLE_MRC_CACHE 408 bool "Enable MRC cache" 409 depends on !EFI && !SYS_COREBOOT 410 help 411 Enable this feature to cause MRC data to be cached in NV storage 412 to be used for speeding up boot time on future reboots and/or 413 power cycles. 414 415 For platforms that use Intel FSP for the memory initialization, 416 please check FSP output HOB via U-Boot command 'fsp hob' to see 417 if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h). 418 If such GUID does not exist, MRC cache is not avaiable on such 419 platform (eg: Intel Queensbay), which means selecting this option 420 here does not make any difference. 421 422 config HAVE_MRC 423 bool "Add a System Agent binary" 424 depends on !HAVE_FSP 425 help 426 Select this option to add a System Agent binary to 427 the resulting U-Boot image. MRC stands for Memory Reference Code. 428 It is a binary blob which U-Boot uses to set up SDRAM. 429 430 Note: Without this binary U-Boot will not be able to set up its 431 SDRAM so will not boot. 432 433 config CACHE_MRC_BIN 434 bool 435 depends on HAVE_MRC 436 default n 437 help 438 Enable caching for the memory reference code binary. This uses an 439 MTRR (memory type range register) to turn on caching for the section 440 of SPI flash that contains the memory reference code. This makes 441 SDRAM init run faster. 442 443 config CACHE_MRC_SIZE_KB 444 int 445 depends on HAVE_MRC 446 default 512 447 help 448 Sets the size of the cached area for the memory reference code. 449 This ends at the end of SPI flash (address 0xffffffff) and is 450 measured in KB. Typically this is set to 512, providing for 0.5MB 451 of cached space. 452 453 config DCACHE_RAM_BASE 454 hex 455 depends on HAVE_MRC 456 help 457 Sets the base of the data cache area in memory space. This is the 458 start address of the cache-as-RAM (CAR) area and the address varies 459 depending on the CPU. Once CAR is set up, read/write memory becomes 460 available at this address and can be used temporarily until SDRAM 461 is working. 462 463 config DCACHE_RAM_SIZE 464 hex 465 depends on HAVE_MRC 466 default 0x40000 467 help 468 Sets the total size of the data cache area in memory space. This 469 sets the size of the cache-as-RAM (CAR) area. Note that much of the 470 CAR space is required by the MRC. The CAR space available to U-Boot 471 is normally at the start and typically extends to 1/4 or 1/2 of the 472 available size. 473 474 config DCACHE_RAM_MRC_VAR_SIZE 475 hex 476 depends on HAVE_MRC 477 help 478 This is the amount of CAR (Cache as RAM) reserved for use by the 479 memory reference code. This depends on the implementation of the 480 memory reference code and must be set correctly or the board will 481 not boot. 482 483 config HAVE_REFCODE 484 bool "Add a Reference Code binary" 485 help 486 Select this option to add a Reference Code binary to the resulting 487 U-Boot image. This is an Intel binary blob that handles system 488 initialisation, in this case the PCH and System Agent. 489 490 Note: Without this binary (on platforms that need it such as 491 broadwell) U-Boot will be missing some critical setup steps. 492 Various peripherals may fail to work. 493 494 config SMP 495 bool "Enable Symmetric Multiprocessing" 496 default n 497 help 498 Enable use of more than one CPU in U-Boot and the Operating System 499 when loaded. Each CPU will be started up and information can be 500 obtained using the 'cpu' command. If this option is disabled, then 501 only one CPU will be enabled regardless of the number of CPUs 502 available. 503 504 config MAX_CPUS 505 int "Maximum number of CPUs permitted" 506 depends on SMP 507 default 4 508 help 509 When using multi-CPU chips it is possible for U-Boot to start up 510 more than one CPU. The stack memory used by all of these CPUs is 511 pre-allocated so at present U-Boot wants to know the maximum 512 number of CPUs that may be present. Set this to at least as high 513 as the number of CPUs in your system (it uses about 4KB of RAM for 514 each CPU). 515 516 config AP_STACK_SIZE 517 hex 518 depends on SMP 519 default 0x1000 520 help 521 Each additional CPU started by U-Boot requires its own stack. This 522 option sets the stack size used by each CPU and directly affects 523 the memory used by this initialisation process. Typically 4KB is 524 enough space. 525 526 config CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED 527 bool 528 help 529 This option indicates that the turbo mode setting is not package 530 scoped. i.e. turbo_enable() needs to be called on not just the 531 bootstrap processor (BSP). 532 533 config HAVE_VGA_BIOS 534 bool "Add a VGA BIOS image" 535 help 536 Select this option if you have a VGA BIOS image that you would 537 like to add to your ROM. 538 539 config VGA_BIOS_FILE 540 string "VGA BIOS image filename" 541 depends on HAVE_VGA_BIOS 542 default "vga.bin" 543 help 544 The filename of the VGA BIOS image in the board directory. 545 546 config VGA_BIOS_ADDR 547 hex "VGA BIOS image location" 548 depends on HAVE_VGA_BIOS 549 default 0xfff90000 550 help 551 The location of VGA BIOS image in the SPI flash. For example, base 552 address of 0xfff90000 indicates that the image will be put at offset 553 0x90000 from the beginning of a 1MB flash device. 554 555 config HAVE_VBT 556 bool "Add a Video BIOS Table (VBT) image" 557 depends on HAVE_FSP 558 help 559 Select this option if you have a Video BIOS Table (VBT) image that 560 you would like to add to your ROM. This is normally required if you 561 are using an Intel FSP firmware that is complaint with spec 1.1 or 562 later to initialize the integrated graphics device (IGD). 563 564 Video BIOS Table, or VBT, provides platform and board specific 565 configuration information to the driver that is not discoverable 566 or available through other means. By other means the most used 567 method here is to read EDID table from the attached monitor, over 568 Display Data Channel (DDC) using two pin I2C serial interface. VBT 569 configuration is related to display hardware and is available via 570 the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM). 571 572 config VBT_FILE 573 string "Video BIOS Table (VBT) image filename" 574 depends on HAVE_VBT 575 default "vbt.bin" 576 help 577 The filename of the file to use as Video BIOS Table (VBT) image 578 in the board directory. 579 580 config VBT_ADDR 581 hex "Video BIOS Table (VBT) image location" 582 depends on HAVE_VBT 583 default 0xfff90000 584 help 585 The location of Video BIOS Table (VBT) image in the SPI flash. For 586 example, base address of 0xfff90000 indicates that the image will 587 be put at offset 0x90000 from the beginning of a 1MB flash device. 588 589 config VIDEO_FSP 590 bool "Enable FSP framebuffer driver support" 591 depends on HAVE_VBT && DM_VIDEO 592 help 593 Turn on this option to enable a framebuffer driver when U-Boot is 594 using Video BIOS Table (VBT) image for FSP firmware to initialize 595 the integrated graphics device. 596 597 config ROM_TABLE_ADDR 598 hex 599 default 0xf0000 600 help 601 All x86 tables happen to like the address range from 0x0f0000 602 to 0x100000. We use 0xf0000 as the starting address to store 603 those tables, including PIRQ routing table, Multi-Processor 604 table and ACPI table. 605 606 config ROM_TABLE_SIZE 607 hex 608 default 0x10000 609 610 menu "System tables" 611 depends on !EFI && !SYS_COREBOOT 612 613 config GENERATE_PIRQ_TABLE 614 bool "Generate a PIRQ table" 615 default n 616 help 617 Generate a PIRQ routing table for this board. The PIRQ routing table 618 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff 619 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR"). 620 It specifies the interrupt router information as well how all the PCI 621 devices' interrupt pins are wired to PIRQs. 622 623 config GENERATE_SFI_TABLE 624 bool "Generate a SFI (Simple Firmware Interface) table" 625 help 626 The Simple Firmware Interface (SFI) provides a lightweight method 627 for platform firmware to pass information to the operating system 628 via static tables in memory. Kernel SFI support is required to 629 boot on SFI-only platforms. If you have ACPI tables then these are 630 used instead. 631 632 U-Boot writes this table in write_sfi_table() just before booting 633 the OS. 634 635 For more information, see http://simplefirmware.org 636 637 config GENERATE_MP_TABLE 638 bool "Generate an MP (Multi-Processor) table" 639 default n 640 help 641 Generate an MP (Multi-Processor) table for this board. The MP table 642 provides a way for the operating system to support for symmetric 643 multiprocessing as well as symmetric I/O interrupt handling with 644 the local APIC and I/O APIC. 645 646 config GENERATE_ACPI_TABLE 647 bool "Generate an ACPI (Advanced Configuration and Power Interface) table" 648 default n 649 select QFW if QEMU 650 help 651 The Advanced Configuration and Power Interface (ACPI) specification 652 provides an open standard for device configuration and management 653 by the operating system. It defines platform-independent interfaces 654 for configuration and power management monitoring. 655 656 endmenu 657 658 config HAVE_ACPI_RESUME 659 bool "Enable ACPI S3 resume" 660 select ENABLE_MRC_CACHE 661 help 662 Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping 663 state where all system context is lost except system memory. U-Boot 664 is responsible for restoring the machine state as it was before sleep. 665 It needs restore the memory controller, without overwriting memory 666 which is not marked as reserved. For the peripherals which lose their 667 registers, U-Boot needs to write the original value. When everything 668 is done, U-Boot needs to find out the wakeup vector provided by OSes 669 and jump there. 670 671 config S3_VGA_ROM_RUN 672 bool "Re-run VGA option ROMs on S3 resume" 673 depends on HAVE_ACPI_RESUME 674 help 675 Execute VGA option ROMs in U-Boot when resuming from S3. Normally 676 this is needed when graphics console is being used in the kernel. 677 678 Turning it off can reduce some resume time, but be aware that your 679 graphics console won't work without VGA options ROMs. Set it to N 680 if your kernel is only on a serial console. 681 682 config STACK_SIZE 683 hex 684 depends on HAVE_ACPI_RESUME 685 default 0x1000 686 help 687 Estimated U-Boot's runtime stack size that needs to be reserved 688 during an ACPI S3 resume. 689 690 config MAX_PIRQ_LINKS 691 int 692 default 8 693 help 694 This variable specifies the number of PIRQ interrupt links which are 695 routable. On most older chipsets, this is 4, PIRQA through PIRQD. 696 Some newer chipsets offer more than four links, commonly up to PIRQH. 697 698 config IRQ_SLOT_COUNT 699 int 700 default 128 701 help 702 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table 703 which in turns forms a table of exact 4KiB. The default value 128 704 should be enough for most boards. If this does not fit your board, 705 change it according to your needs. 706 707 config PCIE_ECAM_BASE 708 hex 709 default 0xe0000000 710 help 711 This is the memory-mapped address of PCI configuration space, which 712 is only available through the Enhanced Configuration Access 713 Mechanism (ECAM) with PCI Express. It can be set up almost 714 anywhere. Before it is set up, it is possible to access PCI 715 configuration space through I/O access, but memory access is more 716 convenient. Using this, PCI can be scanned and configured. This 717 should be set to a region that does not conflict with memory 718 assigned to PCI devices - i.e. the memory and prefetch regions, as 719 passed to pci_set_region(). 720 721 config PCIE_ECAM_SIZE 722 hex 723 default 0x10000000 724 help 725 This is the size of memory-mapped address of PCI configuration space, 726 which is only available through the Enhanced Configuration Access 727 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory, 728 so a default 0x10000000 size covers all of the 256 buses which is the 729 maximum number of PCI buses as defined by the PCI specification. 730 731 config I8259_PIC 732 bool "Enable Intel 8259 compatible interrupt controller" 733 default y 734 help 735 Intel 8259 ISA compatible chipset incorporates two 8259 (master and 736 slave) interrupt controllers. Include this to have U-Boot set up 737 the interrupt correctly. 738 739 config APIC 740 bool "Enable Intel Advanced Programmable Interrupt Controller" 741 default y 742 help 743 The (A)dvanced (P)rogrammable (I)nterrupt (C)ontroller is responsible 744 for catching interrupts and distributing them to one or more CPU 745 cores. In most cases there are some LAPICs (local) for each core and 746 one I/O APIC. This conjunction is found on most modern x86 systems. 747 748 config PINCTRL_ICH6 749 bool 750 help 751 Intel ICH6 compatible chipset pinctrl driver. It needs to work 752 together with the ICH6 compatible gpio driver. 753 754 config I8254_TIMER 755 bool 756 default y 757 help 758 Intel 8254 timer contains three counters which have fixed uses. 759 Include this to have U-Boot set up the timer correctly. 760 761 config SEABIOS 762 bool "Support booting SeaBIOS" 763 help 764 SeaBIOS is an open source implementation of a 16-bit X86 BIOS. 765 It can run in an emulator or natively on X86 hardware with the use 766 of coreboot/U-Boot. By turning on this option, U-Boot prepares 767 all the configuration tables that are necessary to boot SeaBIOS. 768 769 Check http://www.seabios.org/SeaBIOS for details. 770 771 config HIGH_TABLE_SIZE 772 hex "Size of configuration tables which reside in high memory" 773 default 0x10000 774 depends on SEABIOS 775 help 776 SeaBIOS itself resides in E seg and F seg, where U-Boot puts all 777 configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot 778 puts a copy of configuration tables in high memory region which 779 is reserved on the stack before relocation. The region size is 780 determined by this option. 781 782 Increse it if the default size does not fit the board's needs. 783 This is most likely due to a large ACPI DSDT table is used. 784 785 endmenu 786