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Searched refs:ARRAY_FIELD_EX32 (Results 1 – 21 of 21) sorted by relevance

/openbmc/qemu/hw/ssi/
H A Dxlnx-versal-ospi.c337 return ARRAY_FIELD_EX32(s->regs, in ospi_stig_addr_len()
344 return ARRAY_FIELD_EX32(s->regs, in ospi_stig_wr_data_len()
351 return ARRAY_FIELD_EX32(s->regs, in ospi_stig_rd_data_len()
372 return ARRAY_FIELD_EX32(s->regs, in ospi_get_wr_opcode()
378 return ARRAY_FIELD_EX32(s->regs, in ospi_get_rd_opcode()
385 return ARRAY_FIELD_EX32(s->regs, in ospi_get_num_addr_bytes()
391 int idx = ARRAY_FIELD_EX32(s->regs, in ospi_stig_membank_req()
400 int rd_data_fld = ARRAY_FIELD_EX32(s->regs, FLASH_COMMAND_CTRL_MEM_REG, in ospi_stig_membank_rd_bytes()
408 return ARRAY_FIELD_EX32(s->regs, in ospi_get_page_sz()
528 unsigned int block_fld = ARRAY_FIELD_EX32(s->regs, in ospi_get_block_sz()
[all …]
H A Dxilinx_spips.c232 s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); in xilinx_spips_update_cs()
251 int field = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT); in xlnx_zynqmp_qspips_update_cs_lines()
259 buses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT); in xlnx_zynqmp_qspips_update_cs_lines()
470 imm = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); in xlnx_zynqmp_qspips_flush_fifo_g()
471 if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { in xlnx_zynqmp_qspips_flush_fifo_g()
473 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || in xlnx_zynqmp_qspips_flush_fifo_g()
474 ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { in xlnx_zynqmp_qspips_flush_fifo_g()
480 } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, EXPONENT)) { in xlnx_zynqmp_qspips_flush_fifo_g()
494 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE) && in xlnx_zynqmp_qspips_flush_fifo_g()
499 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, STRIPE) && in xlnx_zynqmp_qspips_flush_fifo_g()
[all …]
/openbmc/qemu/hw/net/can/
H A Dxlnx-zynqmp-can.c259 ARRAY_FIELD_EX32(s->regs, WIR, EW)) { in can_update_irq()
264 ARRAY_FIELD_EX32(s->regs, WIR, FW)) { in can_update_irq()
347 bool sleep_status = ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP); in update_status_register_mode_bits()
348 bool sleep_mode = ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP); in update_status_register_mode_bits()
361 if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, LBACK)) { in update_status_register_mode_bits()
363 } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP)) { in update_status_register_mode_bits()
367 } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) { in update_status_register_mode_bits()
406 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) { in tx_ready_check()
415 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) { in tx_ready_check()
425 if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) { in tx_ready_check()
[all …]
H A Dxlnx-versal-canfd.c688 if (ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, FL) > in canfd_update_irq()
689 ARRAY_FIELD_EX32(s->regs, RX_FIFO_WATERMARK_REGISTER, RXFWM)) { in canfd_update_irq()
693 if (ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, FL_1) > in canfd_update_irq()
694 ARRAY_FIELD_EX32(s->regs, RX_FIFO_WATERMARK_REGISTER, RXFWM_1)) { in canfd_update_irq()
699 if (ARRAY_FIELD_EX32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_FL) > in canfd_update_irq()
700 ARRAY_FIELD_EX32(s->regs, TX_EVENT_FIFO_WATERMARK_REGISTER, TXE_FWM)) { in canfd_update_irq()
728 if (ARRAY_FIELD_EX32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL_1)) { in canfd_icr_pre_write()
778 bool sleep_status = ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP); in update_status_register_mode_bits()
779 bool sleep_mode = ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP); in update_status_register_mode_bits()
792 if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, LBACK)) { in update_status_register_mode_bits()
[all …]
/openbmc/qemu/hw/dma/
H A Dxlnx-zdma.c258 cnt = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_SRC_ACCT, CNT); in zdma_src_done()
264 if (cnt != ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_SRC_ACCT, CNT)) { in zdma_src_done()
273 cnt = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_DST_ACCT, CNT); in zdma_dst_done()
279 if (cnt != ARRAY_FIELD_EX32(s->regs, ZDMA_CH_IRQ_DST_ACCT, CNT)) { in zdma_dst_done()
332 unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE); in zdma_load_src_descriptor()
366 unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE); in zdma_load_dst_descriptor()
389 unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE); in zdma_write_dst()
390 unsigned int rw_mode = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, MODE); in zdma_write_dst()
391 unsigned int burst_type = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_DATA_ATTR, in zdma_write_dst()
450 unsigned int ptype = ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_TYPE); in zdma_process_descr()
[all …]
H A Dxlnx_csu_dma.c147 cnt = ARRAY_FIELD_EX32(s->regs, STATUS, DONE_CNT) + a; in xlnx_csu_dma_update_done_cnt()
315 uint32_t timeout = ARRAY_FIELD_EX32(s->regs, CTRL, TIMEOUT_VAL); in xlnx_csu_dma_src_notify()
316 uint32_t div = ARRAY_FIELD_EX32(s->regs, CTRL2, TIMEOUT_PRE) + 1; in xlnx_csu_dma_src_notify()
/openbmc/qemu/hw/misc/
H A Dxlnx-versal-trng.c145 if (ARRAY_FIELD_EX32(s->regs, RESET, VAL)) { in trng_in_reset()
148 if (ARRAY_FIELD_EX32(s->regs, CTRL, PRNGSRST)) { in trng_in_reset()
157 return ARRAY_FIELD_EX32(s->regs, CTRL, TSTMODE); in trng_test_enabled()
165 if (!ARRAY_FIELD_EX32(s->regs, CTRL, TRSSEN)) { in trng_trss_enabled()
168 if (!ARRAY_FIELD_EX32(s->regs, OSC_EN, VAL)) { in trng_trss_enabled()
185 bool ext_seed = ARRAY_FIELD_EX32(s->regs, CTRL, PRNGXS); in trng_reseed()
186 bool pers_disabled = ARRAY_FIELD_EX32(s->regs, CTRL, PERSODISABLE); in trng_reseed()
371 !ARRAY_FIELD_EX32(s->regs, CTRL, QERTUEN)) { in trng_fault_event_set()
446 bool oneshot = ARRAY_FIELD_EX32(s->regs, CTRL, SINGLEGENMODE); in trng_core_out_postr()
447 bool start = ARRAY_FIELD_EX32(s->regs, CTRL, PRNGSTART); in trng_core_out_postr()
[all …]
H A Dxlnx-versal-cframe-reg.c93 uint32_t faddr = ARRAY_FIELD_EX32(s->regs, FAR0, FRAME_ADDR); in cframe_incr_far()
94 uint32_t blktype = ARRAY_FIELD_EX32(s->regs, FAR0, BLOCKTYPE); in cframe_incr_far()
189 uint8_t cmd = ARRAY_FIELD_EX32(s->regs, CMD0, CMD); in cfrm_cmd_post_write()
H A Dxlnx-versal-pmc-iou-slcr.c848 uint32_t prev = ARRAY_FIELD_EX32(s->regs, SD0_CTRL_REG, SD0_EMMC_SEL); in sd0_ctrl_reg_prew()
860 uint32_t prev = ARRAY_FIELD_EX32(s->regs, SD1_CTRL_REG, SD1_EMMC_SEL); in sd1_ctrl_reg_prew()
880 ARRAY_FIELD_EX32(s->regs, OSPI_QSPI_IOU_AXI_MUX_SEL, OSPI_MUX_SEL)) { in ospi_qspi_iou_axi_mux_sel_prew()
885 ARRAY_FIELD_EX32(s->regs, OSPI_QSPI_IOU_AXI_MUX_SEL, in ospi_qspi_iou_axi_mux_sel_prew()
H A Dxlnx-versal-crl.c78 bool old_f = ARRAY_FIELD_EX32((s)->regs, reg, f); \
H A Dxlnx-versal-cfu.c225 if (ARRAY_FIELD_EX32(s->regs, CFU_CTL, DECOMPRESS) == 0) { in cfu_stream_write()
/openbmc/qemu/hw/i3c/
H A Daspeed_i3c.c429 return ARRAY_FIELD_EX32(s->regs, HW_CAPABILITY, ENTDAA); in aspeed_i3c_device_has_entdaa()
434 return ARRAY_FIELD_EX32(s->regs, HW_CAPABILITY, HDR_TS); in aspeed_i3c_device_has_hdr_ts()
439 return ARRAY_FIELD_EX32(s->regs, HW_CAPABILITY, HDR_DDR); in aspeed_i3c_device_has_hdr_ddr()
448 return ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL, I3C_EN) && in aspeed_i3c_device_can_transmit()
449 !ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL, I3C_RESUME); in aspeed_i3c_device_can_transmit()
459 uint8_t ibi_slice_size = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, in aspeed_i3c_device_ibi_slice_size()
655 uint8_t table_size = ARRAY_FIELD_EX32(s->regs, DEVICE_ADDR_TABLE_POINTER, in aspeed_i3c_device_addr_table_index_from_addr()
684 if (ARRAY_FIELD_EX32(s->regs, IBI_QUEUE_CTRL, NOTIFY_REJECTED_HOT_JOIN)) { in aspeed_i3c_device_handle_hj()
688 bool nack_and_disable = ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL, in aspeed_i3c_device_handle_hj()
703 if (ARRAY_FIELD_EX32(s->regs, IBI_QUEUE_CTRL, NOTIFY_REJECTED_MASTER_REQ)) { in aspeed_i3c_device_handle_ctlr_req()
[all …]
/openbmc/qemu/hw/i2c/
H A Daspeed_i2c.c50 ARRAY_FIELD_EX32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE) ? in aspeed_i2c_bus_raise_interrupt()
58 ARRAY_FIELD_EX32(bus->regs, I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH) ? in aspeed_i2c_bus_raise_interrupt()
285 ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN_STS, in aspeed_i2c_bus_send()
355 ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN_STS, in aspeed_i2c_bus_recv()
390 return (ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, PKT_DEV_ADDR) << 1) | in aspeed_i2c_get_addr()
644 if (ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, W1_CTRL)) { in aspeed_i2c_bus_new_write()
659 bus->regs[R_I2CC_DMA_LEN] = ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, in aspeed_i2c_bus_new_write()
668 bus->regs[R_I2CC_DMA_LEN] = ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, in aspeed_i2c_bus_new_write()
724 if (ARRAY_FIELD_EX32(bus->regs, I2CS_INTR_CTRL, PKT_CMD_DONE)) { in aspeed_i2c_bus_new_write()
725 if (ARRAY_FIELD_EX32(bus->regs, I2CS_INTR_STS, PKT_CMD_DONE) && in aspeed_i2c_bus_new_write()
[all …]
/openbmc/qemu/hw/tpm/
H A Dtpm_crb.c108 if (!ARRAY_FIELD_EX32(s->regs, CRB_LOC_STATE, locAssigned)) { in tpm_crb_get_active_locty()
111 return ARRAY_FIELD_EX32(s->regs, CRB_LOC_STATE, activeLocality); in tpm_crb_get_active_locty()
/openbmc/qemu/hw/nvram/
H A Dxlnx-versal-efuse-ctrl.c388 if (!ARRAY_FIELD_EX32(s->regs, CFG, PGM_EN)) { in efuse_pgm_locked()
395 if (ARRAY_FIELD_EX32(s->regs, EFUSE_PGM_LOCK, SPK_ID_LOCK) && in efuse_pgm_locked()
522 val64 |= ARRAY_FIELD_EX32(s->regs, EFUSE_PGM_LOCK, SPK_ID_LOCK); in efuse_pgm_lock_prew()
H A Dxlnx-bbram.c83 return ARRAY_FIELD_EX32(s->regs, BBRAM_MSW_LOCK, VAL) != 0; in bbram_msw_locked()
88 return ARRAY_FIELD_EX32(s->regs, BBRAM_STATUS, PGM_MODE) != 0; in bbram_pgm_enabled()
H A Dxlnx-zynqmp-efuse.c409 if (ARRAY_FIELD_EX32(s->regs, WR_LOCK, LOCK)) { in zynqmp_efuse_pgm_addr_postw()
414 if (!ARRAY_FIELD_EX32(s->regs, CFG, PGM_EN)) { in zynqmp_efuse_pgm_addr_postw()
424 if (ARRAY_FIELD_EX32(s->regs, SEC_CTRL, AES_WRLK) in zynqmp_efuse_pgm_addr_postw()
/openbmc/qemu/include/hw/i2c/
H A Daspeed_i2c.h315 return ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, PKT_OP_EN); in aspeed_i2c_bus_pkt_mode_en()
/openbmc/qemu/include/hw/
H A Dregisterfields.h76 #define ARRAY_FIELD_EX32(regs, reg, field) \ macro
/openbmc/qemu/hw/cxl/
H A Dcxl-device-utils.c182 if (ARRAY_FIELD_EX32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CTRL, in mailbox_reg_write()
/openbmc/qemu/hw/usb/
H A Dhcd-dwc3.c387 if (ARRAY_FIELD_EX32(s->regs, GCTL, CORESOFTRESET)) { in usb_dwc3_gctl_postw()