Home
last modified time | relevance | path

Searched refs:ARRAY_FIELD_DP32 (Results 1 – 20 of 20) sorted by relevance

/openbmc/qemu/hw/tpm/
H A Dtpm_crb.c126 ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, in tpm_crb_mmio_write()
130 ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, in tpm_crb_mmio_write()
164 ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, in tpm_crb_mmio_write()
166 ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, in tpm_crb_mmio_write()
170 ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, in tpm_crb_mmio_write()
172 ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, in tpm_crb_mmio_write()
174 ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, in tpm_crb_mmio_write()
198 ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, in tpm_crb_request_completed()
246 ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, in tpm_crb_reset()
248 ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, in tpm_crb_reset()
[all …]
/openbmc/qemu/hw/cxl/
H A Dcxl-component-utils.c239 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT, in hdm_init_common()
241 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 1); in hdm_init_common()
242 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_256B, 1); in hdm_init_common()
243 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 1); in hdm_init_common()
244 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, in hdm_init_common()
246 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 3_6_12_WAY, 0); in hdm_init_common()
247 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 16_WAY, 0); in hdm_init_common()
248 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, UIO, 0); in hdm_init_common()
249 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, in hdm_init_common()
251 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, MEMDATA_NXM_CAP, 0); in hdm_init_common()
[all …]
H A Dcxl-device-utils.c225 ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CTRL, in mailbox_reg_write()
360 ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP, in mailbox_reg_init_common()
364 ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP, in mailbox_reg_init_common()
366 ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP, in mailbox_reg_init_common()
369 ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP, in mailbox_reg_init_common()
371 ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP, in mailbox_reg_init_common()
/openbmc/qemu/hw/i3c/
H A Daspeed_i3c.c502 ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, in aspeed_i3c_device_send_start()
504 ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS, in aspeed_i3c_device_send_start()
506 ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TRANSFER_ERR, 1); in aspeed_i3c_device_send_start()
507 ARRAY_FIELD_DP32(s->regs, DEVICE_CTRL, I3C_RESUME, 1); in aspeed_i3c_device_send_start()
536 ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, in aspeed_i3c_device_send()
538 ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS, in aspeed_i3c_device_send()
540 ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TRANSFER_ERR, 1); in aspeed_i3c_device_send()
541 ARRAY_FIELD_DP32(s->regs, DEVICE_CTRL, I3C_RESUME, 1); in aspeed_i3c_device_send()
580 ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, in aspeed_i3c_device_recv_data()
582 ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS, in aspeed_i3c_device_recv_data()
[all …]
/openbmc/qemu/hw/net/can/
H A Dxlnx-zynqmp-can.c260 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFWMEMP, 1); in can_update_irq()
265 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL, 1); in can_update_irq()
270 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXNEMP, 1); in can_update_irq()
275 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFEMP, 1); in can_update_irq()
279 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFLL, 1); in can_update_irq()
283 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXBFLL, 1); in can_update_irq()
332 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 1); in can_config_mode()
333 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP, 0); in can_config_mode()
334 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP, 0); in can_config_mode()
335 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, BSOFF, 0); in can_config_mode()
[all …]
H A Dxlnx-versal-canfd.c690 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL, 1); in canfd_update_irq()
695 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL_1, 1); in canfd_update_irq()
701 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXEWMFLL, 1); in canfd_update_irq()
729 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXBOFLW_BI, 0); in canfd_icr_pre_write()
757 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 1); in canfd_config_mode()
758 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP, 0); in canfd_config_mode()
759 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP, 0); in canfd_config_mode()
760 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, BSOFF, 0); in canfd_config_mode()
761 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ERROR_BIT, 0); in canfd_config_mode()
762 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW, 0); in canfd_config_mode()
[all …]
/openbmc/qemu/hw/dma/
H A Dxlnx-zdma.c247 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_STATUS, STATE, state); in zdma_set_state()
251 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_STATUS, STATE, 3); in zdma_set_state()
260 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_IRQ_SRC_ACCT, CNT, cnt); in zdma_src_done()
261 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, SRC_DSCR_DONE, true); in zdma_src_done()
265 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, IRQ_SRC_ACCT_ERR, true); in zdma_src_done()
275 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_IRQ_DST_ACCT, CNT, cnt); in zdma_dst_done()
276 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, DST_DSCR_DONE, true); in zdma_dst_done()
280 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, IRQ_DST_ACCT_ERR, true); in zdma_dst_done()
342 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, AXI_RD_SRC_DSCR, true); in zdma_load_src_descriptor()
377 ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, AXI_RD_DST_DSCR, true); in zdma_load_dst_descriptor()
[all …]
H A Dxlnx_csu_dma.c148 ARRAY_FIELD_DP32(s->regs, STATUS, DONE_CNT, cnt); in xlnx_csu_dma_update_done_cnt()
/openbmc/qemu/hw/nvram/
H A Dxlnx-zynqmp-efuse.c260 ARRAY_FIELD_DP32((s)->regs, reg, field, \
265 ARRAY_FIELD_DP32((s)->regs, reg, field, xlnx_efuse_get_bit((s->efuse), \
436 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 0); in zynqmp_efuse_pgm_addr_postw()
440 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1); in zynqmp_efuse_pgm_addr_postw()
446 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1); in zynqmp_efuse_pgm_addr_postw()
538 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 0); in zynqmp_efuse_rd_addr_postw()
539 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 1); in zynqmp_efuse_rd_addr_postw()
551 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 1); in zynqmp_efuse_rd_addr_postw()
552 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 0); in zynqmp_efuse_rd_addr_postw()
563 ARRAY_FIELD_DP32(s->regs, STATUS, AES_CRC_PASS, (ok ? 1 : 0)); in zynqmp_efuse_aes_crc_postw()
[all …]
H A Dxlnx-bbram.c155 ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, BBRAM_ZEROIZED, 0); in bbram_bdrv_sync()
173 ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, BBRAM_ZEROIZED, 1); in bbram_bdrv_zero()
226 ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, PGM_MODE, 1); in bbram_pgm_mode_postw()
252 ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, AES_CRC_PASS, in bbram_aes_crc_postw()
H A Dxlnx-versal-efuse-ctrl.c459 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1); in efuse_pgm_addr_postw()
462 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1); in efuse_pgm_addr_postw()
492 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 1); in efuse_rd_addr_postw()
495 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 1); in efuse_rd_addr_postw()
507 ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1); in efuse_cache_load_prew()
/openbmc/qemu/hw/i2c/
H A Daspeed_i2c.c271 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, 0); in aspeed_i2c_bus_send()
284 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, TX_LEN, in aspeed_i2c_bus_send()
331 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN, 0); in aspeed_i2c_bus_recv()
354 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN_STS, RX_LEN, in aspeed_i2c_bus_recv()
493 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1); in aspeed_i2c_bus_handle_cmd()
515 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1); in aspeed_i2c_bus_handle_cmd()
516 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE, 1); in aspeed_i2c_bus_handle_cmd()
546 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_FAIL, 1); in aspeed_i2c_bus_handle_cmd()
560 ARRAY_FIELD_DP32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE, 1); in aspeed_i2c_bus_handle_cmd()
680 ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN, in aspeed_i2c_bus_new_write()
[all …]
/openbmc/qemu/hw/misc/
H A Dxlnx-versal-trng.c263 ARRAY_FIELD_DP32(s->regs, STATUS, QCNT, 4); in trng_regen()
273 ARRAY_FIELD_DP32(s->regs, STATUS, QCNT, s->rand_count); in trng_rdout()
329 ARRAY_FIELD_DP32(s->regs, TRNG_ISR, CORE_INT, pending); in trng_core_int_update()
355 ARRAY_FIELD_DP32(s->regs, STATUS, DONE, true); in trng_done()
374 ARRAY_FIELD_DP32(s->regs, STATUS, CERTF, true); in trng_fault_event_set()
380 ARRAY_FIELD_DP32(s->regs, STATUS, DTF, true); in trng_fault_event_set()
394 ARRAY_FIELD_DP32(s->regs, TRNG_ISR, CORE_INT, 0); in trng_soft_reset()
H A Dxlnx-versal-cframe-reg.c106 ARRAY_FIELD_DP32(s->regs, FAR0, BLOCKTYPE, blktype); in cframe_incr_far()
109 ARRAY_FIELD_DP32(s->regs, FAR0, FRAME_ADDR, faddr); in cframe_incr_far()
487 ARRAY_FIELD_DP32(s->regs, CMD0, CMD, pkt->data[0]); in cframe_reg_cfi_transfer_packet()
H A Dxlnx-versal-cfu.c98 ARRAY_FIELD_DP32(s->regs, CFU_STATUS, SCAN_CLEAR_PASS, 1); in cfu_fgcr_postw()
99 ARRAY_FIELD_DP32(s->regs, CFU_STATUS, SCAN_CLEAR_DONE, 1); in cfu_fgcr_postw()
H A Dxlnx-versal-xramc.c137 ARRAY_FIELD_DP32(s->regs, XRAM_IMP, SIZE, s->cfg.encoded_size); in xram_ctrl_reset_enter()
/openbmc/qemu/hw/ssi/
H A Dxlnx-versal-ospi.c394 ARRAY_FIELD_DP32(s->regs, FLASH_COMMAND_CTRL_MEM_REG, in ospi_stig_membank_req()
785 ARRAY_FIELD_DP32(s->regs, INDIRECT_READ_XFER_CTRL_REG, in ind_rd_inc_num_done()
791 ARRAY_FIELD_DP32(s->regs, INDIRECT_READ_XFER_CTRL_REG, in ospi_ind_rd_completed()
850 ARRAY_FIELD_DP32(s->regs, IRQ_STATUS_REG, in ospi_do_ind_read()
864 ARRAY_FIELD_DP32(s->regs, in ospi_do_ind_read()
941 ARRAY_FIELD_DP32(s->regs, INDIRECT_WRITE_XFER_CTRL_REG, in ind_wr_inc_num_done()
947 ARRAY_FIELD_DP32(s->regs, INDIRECT_WRITE_XFER_CTRL_REG, in ospi_ind_wr_completed()
1219 ARRAY_FIELD_DP32(s->regs, FLASH_COMMAND_CTRL_MEM_REG, in flash_cmd_ctrl_mem_reg_post_write()
1233 ARRAY_FIELD_DP32(s->regs, FLASH_CMD_CTRL_REG, CMD_EXEC_FLD, 0); in flash_cmd_ctrl_reg_post_write()
1280 ARRAY_FIELD_DP32(s->regs, INDIRECT_WRITE_XFER_CTRL_REG, START_FLD, 0); in ind_wr_xfer_ctrl_reg_post_write()
[all …]
/openbmc/qemu/hw/pci-bridge/
H A Dpci_expander_bridge.c317 ARRAY_FIELD_DP32(reg_state, CXL_HDM_CAPABILITY_HEADER, ID, 0); in pxb_cxl_dev_reset()
319 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, in pxb_cxl_dev_reset()
H A Dcxl_upstream.c94 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 8); in latch_registers()
/openbmc/qemu/include/hw/
H A Dregisterfields.h152 #define ARRAY_FIELD_DP32(regs, reg, field, val) \ macro