Searched refs:A32 (Results 1 – 13 of 13) sorted by relevance
/openbmc/linux/arch/x86/boot/ |
H A D | cpucheck.c | 57 #define A32(a, b, c, d) (((d) << 24)+((c) << 16)+((b) << 8)+(a)) macro 61 return cpu_vendor[0] == A32('A', 'u', 't', 'h') && in is_amd() 62 cpu_vendor[1] == A32('e', 'n', 't', 'i') && in is_amd() 63 cpu_vendor[2] == A32('c', 'A', 'M', 'D'); in is_amd() 68 return cpu_vendor[0] == A32('C', 'e', 'n', 't') && in is_centaur() 69 cpu_vendor[1] == A32('a', 'u', 'r', 'H') && in is_centaur() 70 cpu_vendor[2] == A32('a', 'u', 'l', 's'); in is_centaur() 75 return cpu_vendor[0] == A32('G', 'e', 'n', 'u') && in is_transmeta() 76 cpu_vendor[1] == A32('i', 'n', 'e', 'T') && in is_transmeta() 77 cpu_vendor[2] == A32('M', 'x', '8', '6'); in is_transmeta() [all …]
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/openbmc/qemu/target/arm/tcg/ |
H A D | neon-ls.decode | 23 # is a simple transformation of the A32 encoding. 24 # More specifically, this file covers instructions where the A32 encoding is 28 # This file works on the A32 encoding only; calling code for T32 has to 29 # transform the insn into the A32 version first.
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H A D | neon-dp.decode | 27 # is a simple transformation of the A32 encoding. 28 # More specifically, this file covers instructions where the A32 encoding is 32 # This file works on the A32 encoding only; calling code for T32 has to 33 # transform the insn into the A32 version first.
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H A D | a32-uncond.decode | 1 # A32 unconditional instructions
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H A D | vfp-uncond.decode | 22 # generally anything matching A32
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H A D | neon-shared.decode | 23 # both A32 and T32.
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H A D | vfp.decode | 22 # generally anything matching A32
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H A D | a32.decode | 1 # A32 conditional instructions
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H A D | t32.decode | 92 # handling them as r13 and r15 accesses with the same semantics as A32).
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/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv8a/ |
H A D | tune-cortexa32.inc | 3 TUNEVALID[cortexa32] = "Enable Cortex-A32 specific processor optimizations"
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/openbmc/linux/arch/arm64/boot/dts/ti/ |
H A D | k3-j784s4-evm.dts | 379 J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */
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/openbmc/qemu/pc-bios/ |
H A D | qemu.rsrc | 450 $"1536 3437 1D9A 0001 0A32 8133 8034 0135" /* .647.ö..¬2Å3Ä4.5 */
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/openbmc/linux/arch/arm64/ |
H A D | Kconfig | 1746 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
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