1f0984d40SFabiano Rosas# AArch32 VFP instruction descriptions (conditional insns) 2f0984d40SFabiano Rosas# 3f0984d40SFabiano Rosas# Copyright (c) 2019 Linaro, Ltd 4f0984d40SFabiano Rosas# 5f0984d40SFabiano Rosas# This library is free software; you can redistribute it and/or 6f0984d40SFabiano Rosas# modify it under the terms of the GNU Lesser General Public 7f0984d40SFabiano Rosas# License as published by the Free Software Foundation; either 8f0984d40SFabiano Rosas# version 2.1 of the License, or (at your option) any later version. 9f0984d40SFabiano Rosas# 10f0984d40SFabiano Rosas# This library is distributed in the hope that it will be useful, 11f0984d40SFabiano Rosas# but WITHOUT ANY WARRANTY; without even the implied warranty of 12f0984d40SFabiano Rosas# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13f0984d40SFabiano Rosas# Lesser General Public License for more details. 14f0984d40SFabiano Rosas# 15f0984d40SFabiano Rosas# You should have received a copy of the GNU Lesser General Public 16f0984d40SFabiano Rosas# License along with this library; if not, see <http://www.gnu.org/licenses/>. 17f0984d40SFabiano Rosas 18f0984d40SFabiano Rosas# 19f0984d40SFabiano Rosas# This file is processed by scripts/decodetree.py 20f0984d40SFabiano Rosas# 21f0984d40SFabiano Rosas# Encodings for the conditional VFP instructions are here: 22f0984d40SFabiano Rosas# generally anything matching A32 23f0984d40SFabiano Rosas# cccc 11.. .... .... .... 101. .... .... 24f0984d40SFabiano Rosas# and T32 25f0984d40SFabiano Rosas# 1110 110. .... .... .... 101. .... .... 26f0984d40SFabiano Rosas# 1110 1110 .... .... .... 101. .... .... 27f0984d40SFabiano Rosas# (but those patterns might also cover some Neon instructions, 28f0984d40SFabiano Rosas# which do not live in this file.) 29f0984d40SFabiano Rosas 30f0984d40SFabiano Rosas# VFP registers have an odd encoding with a four-bit field 31f0984d40SFabiano Rosas# and a one-bit field which are assembled in different orders 32f0984d40SFabiano Rosas# depending on whether the register is double or single precision. 33f0984d40SFabiano Rosas# Each individual instruction function must do the checks for 34f0984d40SFabiano Rosas# "double register selected but CPU does not have double support" 35f0984d40SFabiano Rosas# and "double register number has bit 4 set but CPU does not 36f0984d40SFabiano Rosas# support D16-D31" (which should UNDEF). 37f0984d40SFabiano Rosas%vm_dp 5:1 0:4 38f0984d40SFabiano Rosas%vm_sp 0:4 5:1 39f0984d40SFabiano Rosas%vn_dp 7:1 16:4 40f0984d40SFabiano Rosas%vn_sp 16:4 7:1 41f0984d40SFabiano Rosas%vd_dp 22:1 12:4 42f0984d40SFabiano Rosas%vd_sp 12:4 22:1 43f0984d40SFabiano Rosas 44f0984d40SFabiano Rosas%vmov_idx_b 21:1 5:2 45f0984d40SFabiano Rosas%vmov_idx_h 21:1 6:1 46f0984d40SFabiano Rosas 47f0984d40SFabiano Rosas%vmov_imm 16:4 0:4 48f0984d40SFabiano Rosas 49f0984d40SFabiano Rosas@vfp_dnm_s ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp 50f0984d40SFabiano Rosas@vfp_dnm_d ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp 51f0984d40SFabiano Rosas 52f0984d40SFabiano Rosas@vfp_dm_ss ................................ vm=%vm_sp vd=%vd_sp 53f0984d40SFabiano Rosas@vfp_dm_dd ................................ vm=%vm_dp vd=%vd_dp 54f0984d40SFabiano Rosas@vfp_dm_ds ................................ vm=%vm_sp vd=%vd_dp 55f0984d40SFabiano Rosas@vfp_dm_sd ................................ vm=%vm_dp vd=%vd_sp 56f0984d40SFabiano Rosas 57f0984d40SFabiano Rosas# VMOV scalar to general-purpose register; note that this does 58f0984d40SFabiano Rosas# include some Neon cases. 59f0984d40SFabiano RosasVMOV_to_gp ---- 1110 u:1 1. 1 .... rt:4 1011 ... 1 0000 \ 60f0984d40SFabiano Rosas vn=%vn_dp size=0 index=%vmov_idx_b 61f0984d40SFabiano RosasVMOV_to_gp ---- 1110 u:1 0. 1 .... rt:4 1011 ..1 1 0000 \ 62f0984d40SFabiano Rosas vn=%vn_dp size=1 index=%vmov_idx_h 63f0984d40SFabiano RosasVMOV_to_gp ---- 1110 0 0 index:1 1 .... rt:4 1011 .00 1 0000 \ 64f0984d40SFabiano Rosas vn=%vn_dp size=2 u=0 65f0984d40SFabiano Rosas 66f0984d40SFabiano RosasVMOV_from_gp ---- 1110 0 1. 0 .... rt:4 1011 ... 1 0000 \ 67f0984d40SFabiano Rosas vn=%vn_dp size=0 index=%vmov_idx_b 68f0984d40SFabiano RosasVMOV_from_gp ---- 1110 0 0. 0 .... rt:4 1011 ..1 1 0000 \ 69f0984d40SFabiano Rosas vn=%vn_dp size=1 index=%vmov_idx_h 70f0984d40SFabiano RosasVMOV_from_gp ---- 1110 0 0 index:1 0 .... rt:4 1011 .00 1 0000 \ 71f0984d40SFabiano Rosas vn=%vn_dp size=2 72f0984d40SFabiano Rosas 73f0984d40SFabiano RosasVDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1 1 0000 \ 74f0984d40SFabiano Rosas vn=%vn_dp 75f0984d40SFabiano Rosas 76f0984d40SFabiano RosasVMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000 77f0984d40SFabiano RosasVMOV_half ---- 1110 000 l:1 .... rt:4 1001 . 001 0000 vn=%vn_sp 78f0984d40SFabiano RosasVMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 vn=%vn_sp 79f0984d40SFabiano Rosas 80f0984d40SFabiano RosasVMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... vm=%vm_sp 81f0984d40SFabiano RosasVMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... vm=%vm_dp 82f0984d40SFabiano Rosas 83f0984d40SFabiano RosasVLDR_VSTR_hp ---- 1101 u:1 .0 l:1 rn:4 .... 1001 imm:8 vd=%vd_sp 84f0984d40SFabiano RosasVLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=%vd_sp 85f0984d40SFabiano RosasVLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=%vd_dp 86f0984d40SFabiano Rosas 87f0984d40SFabiano Rosas# We split the load/store multiple up into two patterns to avoid 88f0984d40SFabiano Rosas# overlap with other insns in the "Advanced SIMD load/store and 64-bit move" 89f0984d40SFabiano Rosas# grouping: 90f0984d40SFabiano Rosas# P=0 U=0 W=0 is 64-bit VMOV 91f0984d40SFabiano Rosas# P=1 W=0 is VLDR/VSTR 92f0984d40SFabiano Rosas# P=U W=1 is UNDEF 93f0984d40SFabiano Rosas# leaving P=0 U=1 W=x and P=1 U=0 W=1 for load/store multiple. 94f0984d40SFabiano Rosas# These include FSTM/FLDM. 95f0984d40SFabiano RosasVLDM_VSTM_sp ---- 1100 1 . w:1 l:1 rn:4 .... 1010 imm:8 \ 96f0984d40SFabiano Rosas vd=%vd_sp p=0 u=1 97f0984d40SFabiano RosasVLDM_VSTM_dp ---- 1100 1 . w:1 l:1 rn:4 .... 1011 imm:8 \ 98f0984d40SFabiano Rosas vd=%vd_dp p=0 u=1 99f0984d40SFabiano Rosas 100f0984d40SFabiano RosasVLDM_VSTM_sp ---- 1101 0.1 l:1 rn:4 .... 1010 imm:8 \ 101f0984d40SFabiano Rosas vd=%vd_sp p=1 u=0 w=1 102f0984d40SFabiano RosasVLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \ 103f0984d40SFabiano Rosas vd=%vd_dp p=1 u=0 w=1 104f0984d40SFabiano Rosas 105f0984d40SFabiano Rosas# 3-register VFP data-processing; bits [23,21:20,6] identify the operation. 106f0984d40SFabiano RosasVMLA_hp ---- 1110 0.00 .... .... 1001 .0.0 .... @vfp_dnm_s 107f0984d40SFabiano RosasVMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... @vfp_dnm_s 108f0984d40SFabiano RosasVMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... @vfp_dnm_d 109f0984d40SFabiano Rosas 110f0984d40SFabiano RosasVMLS_hp ---- 1110 0.00 .... .... 1001 .1.0 .... @vfp_dnm_s 111f0984d40SFabiano RosasVMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... @vfp_dnm_s 112f0984d40SFabiano RosasVMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... @vfp_dnm_d 113f0984d40SFabiano Rosas 114f0984d40SFabiano RosasVNMLS_hp ---- 1110 0.01 .... .... 1001 .0.0 .... @vfp_dnm_s 115f0984d40SFabiano RosasVNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... @vfp_dnm_s 116f0984d40SFabiano RosasVNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... @vfp_dnm_d 117f0984d40SFabiano Rosas 118f0984d40SFabiano RosasVNMLA_hp ---- 1110 0.01 .... .... 1001 .1.0 .... @vfp_dnm_s 119f0984d40SFabiano RosasVNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... @vfp_dnm_s 120f0984d40SFabiano RosasVNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... @vfp_dnm_d 121f0984d40SFabiano Rosas 122f0984d40SFabiano RosasVMUL_hp ---- 1110 0.10 .... .... 1001 .0.0 .... @vfp_dnm_s 123f0984d40SFabiano RosasVMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... @vfp_dnm_s 124f0984d40SFabiano RosasVMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... @vfp_dnm_d 125f0984d40SFabiano Rosas 126f0984d40SFabiano RosasVNMUL_hp ---- 1110 0.10 .... .... 1001 .1.0 .... @vfp_dnm_s 127f0984d40SFabiano RosasVNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... @vfp_dnm_s 128f0984d40SFabiano RosasVNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... @vfp_dnm_d 129f0984d40SFabiano Rosas 130f0984d40SFabiano RosasVADD_hp ---- 1110 0.11 .... .... 1001 .0.0 .... @vfp_dnm_s 131f0984d40SFabiano RosasVADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... @vfp_dnm_s 132f0984d40SFabiano RosasVADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... @vfp_dnm_d 133f0984d40SFabiano Rosas 134f0984d40SFabiano RosasVSUB_hp ---- 1110 0.11 .... .... 1001 .1.0 .... @vfp_dnm_s 135f0984d40SFabiano RosasVSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... @vfp_dnm_s 136f0984d40SFabiano RosasVSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... @vfp_dnm_d 137f0984d40SFabiano Rosas 138f0984d40SFabiano RosasVDIV_hp ---- 1110 1.00 .... .... 1001 .0.0 .... @vfp_dnm_s 139f0984d40SFabiano RosasVDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s 140f0984d40SFabiano RosasVDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d 141f0984d40SFabiano Rosas 142f0984d40SFabiano RosasVFMA_hp ---- 1110 1.10 .... .... 1001 .0. 0 .... @vfp_dnm_s 143f0984d40SFabiano RosasVFMS_hp ---- 1110 1.10 .... .... 1001 .1. 0 .... @vfp_dnm_s 144*76dd3666SPeter MaydellVFNMS_hp ---- 1110 1.01 .... .... 1001 .0. 0 .... @vfp_dnm_s 145*76dd3666SPeter MaydellVFNMA_hp ---- 1110 1.01 .... .... 1001 .1. 0 .... @vfp_dnm_s 146f0984d40SFabiano Rosas 147f0984d40SFabiano RosasVFMA_sp ---- 1110 1.10 .... .... 1010 .0. 0 .... @vfp_dnm_s 148f0984d40SFabiano RosasVFMS_sp ---- 1110 1.10 .... .... 1010 .1. 0 .... @vfp_dnm_s 149*76dd3666SPeter MaydellVFNMS_sp ---- 1110 1.01 .... .... 1010 .0. 0 .... @vfp_dnm_s 150*76dd3666SPeter MaydellVFNMA_sp ---- 1110 1.01 .... .... 1010 .1. 0 .... @vfp_dnm_s 151f0984d40SFabiano Rosas 152f0984d40SFabiano RosasVFMA_dp ---- 1110 1.10 .... .... 1011 .0.0 .... @vfp_dnm_d 153f0984d40SFabiano RosasVFMS_dp ---- 1110 1.10 .... .... 1011 .1.0 .... @vfp_dnm_d 154*76dd3666SPeter MaydellVFNMS_dp ---- 1110 1.01 .... .... 1011 .0.0 .... @vfp_dnm_d 155*76dd3666SPeter MaydellVFNMA_dp ---- 1110 1.01 .... .... 1011 .1.0 .... @vfp_dnm_d 156f0984d40SFabiano Rosas 157f0984d40SFabiano RosasVMOV_imm_hp ---- 1110 1.11 .... .... 1001 0000 .... \ 158f0984d40SFabiano Rosas vd=%vd_sp imm=%vmov_imm 159f0984d40SFabiano RosasVMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \ 160f0984d40SFabiano Rosas vd=%vd_sp imm=%vmov_imm 161f0984d40SFabiano RosasVMOV_imm_dp ---- 1110 1.11 .... .... 1011 0000 .... \ 162f0984d40SFabiano Rosas vd=%vd_dp imm=%vmov_imm 163f0984d40SFabiano Rosas 164f0984d40SFabiano RosasVMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... @vfp_dm_ss 165f0984d40SFabiano RosasVMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... @vfp_dm_dd 166f0984d40SFabiano Rosas 167f0984d40SFabiano RosasVABS_hp ---- 1110 1.11 0000 .... 1001 11.0 .... @vfp_dm_ss 168f0984d40SFabiano RosasVABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... @vfp_dm_ss 169f0984d40SFabiano RosasVABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... @vfp_dm_dd 170f0984d40SFabiano Rosas 171f0984d40SFabiano RosasVNEG_hp ---- 1110 1.11 0001 .... 1001 01.0 .... @vfp_dm_ss 172f0984d40SFabiano RosasVNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... @vfp_dm_ss 173f0984d40SFabiano RosasVNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... @vfp_dm_dd 174f0984d40SFabiano Rosas 175f0984d40SFabiano RosasVSQRT_hp ---- 1110 1.11 0001 .... 1001 11.0 .... @vfp_dm_ss 176f0984d40SFabiano RosasVSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... @vfp_dm_ss 177f0984d40SFabiano RosasVSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... @vfp_dm_dd 178f0984d40SFabiano Rosas 179f0984d40SFabiano RosasVCMP_hp ---- 1110 1.11 010 z:1 .... 1001 e:1 1.0 .... \ 180f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_sp 181f0984d40SFabiano RosasVCMP_sp ---- 1110 1.11 010 z:1 .... 1010 e:1 1.0 .... \ 182f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_sp 183f0984d40SFabiano RosasVCMP_dp ---- 1110 1.11 010 z:1 .... 1011 e:1 1.0 .... \ 184f0984d40SFabiano Rosas vd=%vd_dp vm=%vm_dp 185f0984d40SFabiano Rosas 186f0984d40SFabiano Rosas# VCVTT and VCVTB from f16: Vd format depends on size bit; Vm is always vm_sp 187f0984d40SFabiano RosasVCVT_f32_f16 ---- 1110 1.11 0010 .... 1010 t:1 1.0 .... \ 188f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_sp 189f0984d40SFabiano RosasVCVT_f64_f16 ---- 1110 1.11 0010 .... 1011 t:1 1.0 .... \ 190f0984d40SFabiano Rosas vd=%vd_dp vm=%vm_sp 191f0984d40SFabiano Rosas 192f0984d40SFabiano Rosas# VCVTB and VCVTT to f16: Vd format is always vd_sp; 193f0984d40SFabiano Rosas# Vm format depends on size bit 194f0984d40SFabiano RosasVCVT_b16_f32 ---- 1110 1.11 0011 .... 1001 t:1 1.0 .... \ 195f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_sp 196f0984d40SFabiano RosasVCVT_f16_f32 ---- 1110 1.11 0011 .... 1010 t:1 1.0 .... \ 197f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_sp 198f0984d40SFabiano RosasVCVT_f16_f64 ---- 1110 1.11 0011 .... 1011 t:1 1.0 .... \ 199f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_dp 200f0984d40SFabiano Rosas 201f0984d40SFabiano RosasVRINTR_hp ---- 1110 1.11 0110 .... 1001 01.0 .... @vfp_dm_ss 202f0984d40SFabiano RosasVRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... @vfp_dm_ss 203f0984d40SFabiano RosasVRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... @vfp_dm_dd 204f0984d40SFabiano Rosas 205f0984d40SFabiano RosasVRINTZ_hp ---- 1110 1.11 0110 .... 1001 11.0 .... @vfp_dm_ss 206f0984d40SFabiano RosasVRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... @vfp_dm_ss 207f0984d40SFabiano RosasVRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... @vfp_dm_dd 208f0984d40SFabiano Rosas 209f0984d40SFabiano RosasVRINTX_hp ---- 1110 1.11 0111 .... 1001 01.0 .... @vfp_dm_ss 210f0984d40SFabiano RosasVRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... @vfp_dm_ss 211f0984d40SFabiano RosasVRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... @vfp_dm_dd 212f0984d40SFabiano Rosas 213f0984d40SFabiano Rosas# VCVT between single and double: 214f0984d40SFabiano Rosas# Vm precision depends on size; Vd is its reverse 215f0984d40SFabiano RosasVCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... @vfp_dm_ds 216f0984d40SFabiano RosasVCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... @vfp_dm_sd 217f0984d40SFabiano Rosas 218f0984d40SFabiano Rosas# VCVT from integer to floating point: Vm always single; Vd depends on size 219f0984d40SFabiano RosasVCVT_int_hp ---- 1110 1.11 1000 .... 1001 s:1 1.0 .... \ 220f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_sp 221f0984d40SFabiano RosasVCVT_int_sp ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \ 222f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_sp 223f0984d40SFabiano RosasVCVT_int_dp ---- 1110 1.11 1000 .... 1011 s:1 1.0 .... \ 224f0984d40SFabiano Rosas vd=%vd_dp vm=%vm_sp 225f0984d40SFabiano Rosas 226f0984d40SFabiano Rosas# VJCVT is always dp to sp 227f0984d40SFabiano RosasVJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... @vfp_dm_sd 228f0984d40SFabiano Rosas 229f0984d40SFabiano Rosas# VCVT between floating-point and fixed-point. The immediate value 230f0984d40SFabiano Rosas# is in the same format as a Vm single-precision register number. 231f0984d40SFabiano Rosas# We assemble bits 18 (op), 16 (u) and 7 (sx) into a single opc field 232f0984d40SFabiano Rosas# for the convenience of the trans_VCVT_fix functions. 233f0984d40SFabiano Rosas%vcvt_fix_op 18:1 16:1 7:1 234f0984d40SFabiano RosasVCVT_fix_hp ---- 1110 1.11 1.1. .... 1001 .1.0 .... \ 235f0984d40SFabiano Rosas vd=%vd_sp imm=%vm_sp opc=%vcvt_fix_op 236f0984d40SFabiano RosasVCVT_fix_sp ---- 1110 1.11 1.1. .... 1010 .1.0 .... \ 237f0984d40SFabiano Rosas vd=%vd_sp imm=%vm_sp opc=%vcvt_fix_op 238f0984d40SFabiano RosasVCVT_fix_dp ---- 1110 1.11 1.1. .... 1011 .1.0 .... \ 239f0984d40SFabiano Rosas vd=%vd_dp imm=%vm_sp opc=%vcvt_fix_op 240f0984d40SFabiano Rosas 241f0984d40SFabiano Rosas# VCVT float to integer (VCVT and VCVTR): Vd always single; Vd depends on size 242f0984d40SFabiano RosasVCVT_hp_int ---- 1110 1.11 110 s:1 .... 1001 rz:1 1.0 .... \ 243f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_sp 244f0984d40SFabiano RosasVCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 .... \ 245f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_sp 246f0984d40SFabiano RosasVCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \ 247f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_dp 248