1*f0984d40SFabiano Rosas# AArch32 VFP instruction descriptions (unconditional insns) 2*f0984d40SFabiano Rosas# 3*f0984d40SFabiano Rosas# Copyright (c) 2019 Linaro, Ltd 4*f0984d40SFabiano Rosas# 5*f0984d40SFabiano Rosas# This library is free software; you can redistribute it and/or 6*f0984d40SFabiano Rosas# modify it under the terms of the GNU Lesser General Public 7*f0984d40SFabiano Rosas# License as published by the Free Software Foundation; either 8*f0984d40SFabiano Rosas# version 2.1 of the License, or (at your option) any later version. 9*f0984d40SFabiano Rosas# 10*f0984d40SFabiano Rosas# This library is distributed in the hope that it will be useful, 11*f0984d40SFabiano Rosas# but WITHOUT ANY WARRANTY; without even the implied warranty of 12*f0984d40SFabiano Rosas# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13*f0984d40SFabiano Rosas# Lesser General Public License for more details. 14*f0984d40SFabiano Rosas# 15*f0984d40SFabiano Rosas# You should have received a copy of the GNU Lesser General Public 16*f0984d40SFabiano Rosas# License along with this library; if not, see <http://www.gnu.org/licenses/>. 17*f0984d40SFabiano Rosas 18*f0984d40SFabiano Rosas# 19*f0984d40SFabiano Rosas# This file is processed by scripts/decodetree.py 20*f0984d40SFabiano Rosas# 21*f0984d40SFabiano Rosas# Encodings for the unconditional VFP instructions are here: 22*f0984d40SFabiano Rosas# generally anything matching A32 23*f0984d40SFabiano Rosas# 1111 1110 .... .... .... 101. ...0 .... 24*f0984d40SFabiano Rosas# and T32 25*f0984d40SFabiano Rosas# 1111 110. .... .... .... 101. .... .... 26*f0984d40SFabiano Rosas# 1111 1110 .... .... .... 101. .... .... 27*f0984d40SFabiano Rosas# (but those patterns might also cover some Neon instructions, 28*f0984d40SFabiano Rosas# which do not live in this file.) 29*f0984d40SFabiano Rosas 30*f0984d40SFabiano Rosas# VFP registers have an odd encoding with a four-bit field 31*f0984d40SFabiano Rosas# and a one-bit field which are assembled in different orders 32*f0984d40SFabiano Rosas# depending on whether the register is double or single precision. 33*f0984d40SFabiano Rosas# Each individual instruction function must do the checks for 34*f0984d40SFabiano Rosas# "double register selected but CPU does not have double support" 35*f0984d40SFabiano Rosas# and "double register number has bit 4 set but CPU does not 36*f0984d40SFabiano Rosas# support D16-D31" (which should UNDEF). 37*f0984d40SFabiano Rosas%vm_dp 5:1 0:4 38*f0984d40SFabiano Rosas%vm_sp 0:4 5:1 39*f0984d40SFabiano Rosas%vn_dp 7:1 16:4 40*f0984d40SFabiano Rosas%vn_sp 16:4 7:1 41*f0984d40SFabiano Rosas%vd_dp 22:1 12:4 42*f0984d40SFabiano Rosas%vd_sp 12:4 22:1 43*f0984d40SFabiano Rosas 44*f0984d40SFabiano Rosas@vfp_dnm_s ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp 45*f0984d40SFabiano Rosas@vfp_dnm_d ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp 46*f0984d40SFabiano Rosas 47*f0984d40SFabiano RosasVSEL 1111 1110 0. cc:2 .... .... 1001 .0.0 .... \ 48*f0984d40SFabiano Rosas vm=%vm_sp vn=%vn_sp vd=%vd_sp sz=1 49*f0984d40SFabiano RosasVSEL 1111 1110 0. cc:2 .... .... 1010 .0.0 .... \ 50*f0984d40SFabiano Rosas vm=%vm_sp vn=%vn_sp vd=%vd_sp sz=2 51*f0984d40SFabiano RosasVSEL 1111 1110 0. cc:2 .... .... 1011 .0.0 .... \ 52*f0984d40SFabiano Rosas vm=%vm_dp vn=%vn_dp vd=%vd_dp sz=3 53*f0984d40SFabiano Rosas 54*f0984d40SFabiano RosasVMAXNM_hp 1111 1110 1.00 .... .... 1001 .0.0 .... @vfp_dnm_s 55*f0984d40SFabiano RosasVMINNM_hp 1111 1110 1.00 .... .... 1001 .1.0 .... @vfp_dnm_s 56*f0984d40SFabiano Rosas 57*f0984d40SFabiano RosasVMAXNM_sp 1111 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s 58*f0984d40SFabiano RosasVMINNM_sp 1111 1110 1.00 .... .... 1010 .1.0 .... @vfp_dnm_s 59*f0984d40SFabiano Rosas 60*f0984d40SFabiano RosasVMAXNM_dp 1111 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d 61*f0984d40SFabiano RosasVMINNM_dp 1111 1110 1.00 .... .... 1011 .1.0 .... @vfp_dnm_d 62*f0984d40SFabiano Rosas 63*f0984d40SFabiano RosasVRINT 1111 1110 1.11 10 rm:2 .... 1001 01.0 .... \ 64*f0984d40SFabiano Rosas vm=%vm_sp vd=%vd_sp sz=1 65*f0984d40SFabiano RosasVRINT 1111 1110 1.11 10 rm:2 .... 1010 01.0 .... \ 66*f0984d40SFabiano Rosas vm=%vm_sp vd=%vd_sp sz=2 67*f0984d40SFabiano RosasVRINT 1111 1110 1.11 10 rm:2 .... 1011 01.0 .... \ 68*f0984d40SFabiano Rosas vm=%vm_dp vd=%vd_dp sz=3 69*f0984d40SFabiano Rosas 70*f0984d40SFabiano Rosas# VCVT float to int with specified rounding mode; Vd is always single-precision 71*f0984d40SFabiano RosasVCVT 1111 1110 1.11 11 rm:2 .... 1001 op:1 1.0 .... \ 72*f0984d40SFabiano Rosas vm=%vm_sp vd=%vd_sp sz=1 73*f0984d40SFabiano RosasVCVT 1111 1110 1.11 11 rm:2 .... 1010 op:1 1.0 .... \ 74*f0984d40SFabiano Rosas vm=%vm_sp vd=%vd_sp sz=2 75*f0984d40SFabiano RosasVCVT 1111 1110 1.11 11 rm:2 .... 1011 op:1 1.0 .... \ 76*f0984d40SFabiano Rosas vm=%vm_dp vd=%vd_sp sz=3 77*f0984d40SFabiano Rosas 78*f0984d40SFabiano RosasVMOVX 1111 1110 1.11 0000 .... 1010 01 . 0 .... \ 79*f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_sp 80*f0984d40SFabiano Rosas 81*f0984d40SFabiano RosasVINS 1111 1110 1.11 0000 .... 1010 11 . 0 .... \ 82*f0984d40SFabiano Rosas vd=%vd_sp vm=%vm_sp 83