Searched hist:de9ac9a1b9c0899d05d582917330092d577d5ebe (Results 1 – 7 of 7) sorted by relevance
| /openbmc/u-boot/arch/x86/cpu/braswell/ |
| H A D | early_uart.c | de9ac9a1b9c0899d05d582917330092d577d5ebe Wed Aug 16 00:41:58 CDT 2017 Bin Meng <bmeng.cn@gmail.com> x86: Add Intel Braswell SoC support
This adds initial Intel Braswell SoC support. It uses Intel FSP
to initialize the chipset.
Similar to its predecessor BayTrail, there are some work to do to
enable the legacy UART integrated in the Braswell SoC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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| H A D | braswell.c | de9ac9a1b9c0899d05d582917330092d577d5ebe Wed Aug 16 00:41:58 CDT 2017 Bin Meng <bmeng.cn@gmail.com> x86: Add Intel Braswell SoC support
This adds initial Intel Braswell SoC support. It uses Intel FSP
to initialize the chipset.
Similar to its predecessor BayTrail, there are some work to do to
enable the legacy UART integrated in the Braswell SoC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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| H A D | Kconfig | de9ac9a1b9c0899d05d582917330092d577d5ebe Wed Aug 16 00:41:58 CDT 2017 Bin Meng <bmeng.cn@gmail.com> x86: Add Intel Braswell SoC support
This adds initial Intel Braswell SoC support. It uses Intel FSP
to initialize the chipset.
Similar to its predecessor BayTrail, there are some work to do to
enable the legacy UART integrated in the Braswell SoC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
|
| H A D | Makefile | de9ac9a1b9c0899d05d582917330092d577d5ebe Wed Aug 16 00:41:58 CDT 2017 Bin Meng <bmeng.cn@gmail.com> x86: Add Intel Braswell SoC support
This adds initial Intel Braswell SoC support. It uses Intel FSP
to initialize the chipset.
Similar to its predecessor BayTrail, there are some work to do to
enable the legacy UART integrated in the Braswell SoC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
|
| /openbmc/u-boot/arch/x86/include/asm/arch-braswell/ |
| H A D | iomap.h | de9ac9a1b9c0899d05d582917330092d577d5ebe Wed Aug 16 00:41:58 CDT 2017 Bin Meng <bmeng.cn@gmail.com> x86: Add Intel Braswell SoC support
This adds initial Intel Braswell SoC support. It uses Intel FSP
to initialize the chipset.
Similar to its predecessor BayTrail, there are some work to do to
enable the legacy UART integrated in the Braswell SoC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
|
| /openbmc/u-boot/arch/x86/cpu/ |
| H A D | Makefile | diff de9ac9a1b9c0899d05d582917330092d577d5ebe Wed Aug 16 00:41:58 CDT 2017 Bin Meng <bmeng.cn@gmail.com> x86: Add Intel Braswell SoC support
This adds initial Intel Braswell SoC support. It uses Intel FSP
to initialize the chipset.
Similar to its predecessor BayTrail, there are some work to do to
enable the legacy UART integrated in the Braswell SoC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
|
| /openbmc/u-boot/arch/x86/ |
| H A D | Kconfig | diff de9ac9a1b9c0899d05d582917330092d577d5ebe Wed Aug 16 00:41:58 CDT 2017 Bin Meng <bmeng.cn@gmail.com> x86: Add Intel Braswell SoC support
This adds initial Intel Braswell SoC support. It uses Intel FSP
to initialize the chipset.
Similar to its predecessor BayTrail, there are some work to do to
enable the legacy UART integrated in the Braswell SoC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
|