Searched hist:"597 a68ce32167e7d07bf40648e1501f786f60f99" (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/drivers/net/ethernet/stmicro/stmmac/ |
| H A D | stmmac_mdio.c | diff 597a68ce32167e7d07bf40648e1501f786f60f99 Mon Jun 07 22:51:56 CDT 2021 Voon Weifeng <weifeng.voon@intel.com> net: stmmac: split xPCS setup from mdio register
This patch is a preparation patch for the enabling of Intel mGbE 2.5Gbps
link speed. The Intel mGbR link speed configuration (1G/2.5G) is depends on
a mdio ADHOC register which can be configured in the bios menu.
As PHY interface might be different for 1G and 2.5G, the mdio bus need be
ready to check the link speed and select the PHY interface before probing
the xPCS.
Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
Signed-off-by: Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| H A D | stmmac.h | diff 597a68ce32167e7d07bf40648e1501f786f60f99 Mon Jun 07 22:51:56 CDT 2021 Voon Weifeng <weifeng.voon@intel.com> net: stmmac: split xPCS setup from mdio register
This patch is a preparation patch for the enabling of Intel mGbE 2.5Gbps
link speed. The Intel mGbR link speed configuration (1G/2.5G) is depends on
a mdio ADHOC register which can be configured in the bios menu.
As PHY interface might be different for 1G and 2.5G, the mdio bus need be
ready to check the link speed and select the PHY interface before probing
the xPCS.
Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
Signed-off-by: Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| H A D | stmmac_main.c | diff 597a68ce32167e7d07bf40648e1501f786f60f99 Mon Jun 07 22:51:56 CDT 2021 Voon Weifeng <weifeng.voon@intel.com> net: stmmac: split xPCS setup from mdio register
This patch is a preparation patch for the enabling of Intel mGbE 2.5Gbps
link speed. The Intel mGbR link speed configuration (1G/2.5G) is depends on
a mdio ADHOC register which can be configured in the bios menu.
As PHY interface might be different for 1G and 2.5G, the mdio bus need be
ready to check the link speed and select the PHY interface before probing
the xPCS.
Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
Signed-off-by: Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|