"1d831cade71883d0578e9f41d19d09b67f8263ac" (history) in projects: openbmc

Searched hist:"1 d831cade71883d0578e9f41d19d09b67f8263ac" (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A D	zynqmp-zcu1275-revA.dts	diff 1d831cade71883d0578e9f41d19d09b67f8263ac Mon May 22 09:59:50 CDT 2023 Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> arm64: zynqmp: Set qspi tx-buswidth to 4 All ZynqMP boards are setting up tx-buswidth to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4. Using all 4 lines will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1f1b0028106d83aa06e0777e91862a07df100fa1.1684767562.git.michal.simek@amd.com
H A D	zynqmp-zc1254-revA.dts	diff 1d831cade71883d0578e9f41d19d09b67f8263ac Mon May 22 09:59:50 CDT 2023 Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> arm64: zynqmp: Set qspi tx-buswidth to 4 All ZynqMP boards are setting up tx-buswidth to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4. Using all 4 lines will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1f1b0028106d83aa06e0777e91862a07df100fa1.1684767562.git.michal.simek@amd.com
H A D	zynqmp-zc1751-xm018-dc4.dts	diff 1d831cade71883d0578e9f41d19d09b67f8263ac Mon May 22 09:59:50 CDT 2023 Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> arm64: zynqmp: Set qspi tx-buswidth to 4 All ZynqMP boards are setting up tx-buswidth to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4. Using all 4 lines will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1f1b0028106d83aa06e0777e91862a07df100fa1.1684767562.git.michal.simek@amd.com
H A D	zynqmp-zc1232-revA.dts	diff 1d831cade71883d0578e9f41d19d09b67f8263ac Mon May 22 09:59:50 CDT 2023 Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> arm64: zynqmp: Set qspi tx-buswidth to 4 All ZynqMP boards are setting up tx-buswidth to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4. Using all 4 lines will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1f1b0028106d83aa06e0777e91862a07df100fa1.1684767562.git.michal.simek@amd.com
H A D	zynqmp-zcu104-revC.dts	diff 1d831cade71883d0578e9f41d19d09b67f8263ac Mon May 22 09:59:50 CDT 2023 Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> arm64: zynqmp: Set qspi tx-buswidth to 4 All ZynqMP boards are setting up tx-buswidth to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4. Using all 4 lines will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1f1b0028106d83aa06e0777e91862a07df100fa1.1684767562.git.michal.simek@amd.com
H A D	zynqmp-sm-k26-revA.dts	diff 1d831cade71883d0578e9f41d19d09b67f8263ac Mon May 22 09:59:50 CDT 2023 Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> arm64: zynqmp: Set qspi tx-buswidth to 4 All ZynqMP boards are setting up tx-buswidth to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4. Using all 4 lines will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1f1b0028106d83aa06e0777e91862a07df100fa1.1684767562.git.michal.simek@amd.com
H A D	zynqmp-zc1751-xm015-dc1.dts	diff 1d831cade71883d0578e9f41d19d09b67f8263ac Mon May 22 09:59:50 CDT 2023 Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> arm64: zynqmp: Set qspi tx-buswidth to 4 All ZynqMP boards are setting up tx-buswidth to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4. Using all 4 lines will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1f1b0028106d83aa06e0777e91862a07df100fa1.1684767562.git.michal.simek@amd.com
H A D	zynqmp-zcu104-revA.dts	diff 1d831cade71883d0578e9f41d19d09b67f8263ac Mon May 22 09:59:50 CDT 2023 Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> arm64: zynqmp: Set qspi tx-buswidth to 4 All ZynqMP boards are setting up tx-buswidth to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4. Using all 4 lines will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1f1b0028106d83aa06e0777e91862a07df100fa1.1684767562.git.michal.simek@amd.com
H A D	zynqmp-zcu111-revA.dts	diff 1d831cade71883d0578e9f41d19d09b67f8263ac Mon May 22 09:59:50 CDT 2023 Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> arm64: zynqmp: Set qspi tx-buswidth to 4 All ZynqMP boards are setting up tx-buswidth to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4. Using all 4 lines will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1f1b0028106d83aa06e0777e91862a07df100fa1.1684767562.git.michal.simek@amd.com
H A D	zynqmp-zcu106-revA.dts	diff 1d831cade71883d0578e9f41d19d09b67f8263ac Mon May 22 09:59:50 CDT 2023 Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> arm64: zynqmp: Set qspi tx-buswidth to 4 All ZynqMP boards are setting up tx-buswidth to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4. Using all 4 lines will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1f1b0028106d83aa06e0777e91862a07df100fa1.1684767562.git.michal.simek@amd.com
H A D	zynqmp-zcu102-revA.dts	diff 1d831cade71883d0578e9f41d19d09b67f8263ac Mon May 22 09:59:50 CDT 2023 Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> arm64: zynqmp: Set qspi tx-buswidth to 4 All ZynqMP boards are setting up tx-buswidth to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4. Using all 4 lines will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1f1b0028106d83aa06e0777e91862a07df100fa1.1684767562.git.michal.simek@amd.com

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