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/openbmc/linux/Documentation/devicetree/bindings/fpga/
H A Dxilinx-zynq-fpga-mgr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xilinx-zynq-fpga-mgr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq FPGA Manager
10 - Michal Simek <michal.simek@amd.com>
14 const: xlnx,zynq-devcfg-1.0
17 maxItems: 1
20 maxItems: 1
23 maxItems: 1
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H A Dfpga-region.txt6 - Introduction
7 - Terminology
8 - Sequence
9 - FPGA Region
10 - Supported Use Models
11 - Device Tree Examples
12 - Constraints
82 ---------------- ----------------------------------
85 | ----| | ----------- -------- |
87 | | W | | | ----------- -------- |
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/openbmc/u-boot/arch/arm/dts/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Xilinx Zynq 7000 DTSI
4 * Describes the hardware common to all Zynq 7000-based boards.
6 * Copyright (C) 2011 - 2015 Xilinx
10 #address-cells = <1>;
11 #size-cells = <1>;
12 compatible = "xlnx,zynq-7000";
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
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/openbmc/linux/arch/arm/mach-zynq/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk/zynq.h>
24 #include <linux/irqchip/arm-gic.h>
32 #include <asm/mach-types.h>
36 #include <asm/hardware/cache-l2x0.h>
47 * zynq_memory_init - Initialize special memory
50 * the 1st 512K of memory.
59 .name = "cpuidle-zynq",
63 * zynq_get_revision - Get Zynq silicon revision
65 * Return: Silicon version or -1 otherwise
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/openbmc/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
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/openbmc/qemu/hw/dma/
H A Dxlnx-zynq-devcfg.c2 * QEMU model of the Xilinx Zynq Devcfg Interface
28 #include "hw/dma/xlnx-zynq-devcfg.h"
51 FIELD(CTRL, FORCE_RST, 31, 1) /* Not supported, wr ignored */
52 FIELD(CTRL, PCAP_PR, 27, 1) /* Forced to 0 on bad unlock */
53 FIELD(CTRL, PCAP_MODE, 26, 1)
54 FIELD(CTRL, MULTIBOOT_EN, 24, 1)
55 FIELD(CTRL, USER_MODE, 15, 1)
56 FIELD(CTRL, PCFG_AES_FUSE, 12, 1)
58 FIELD(CTRL, SEU_EN, 8, 1)
59 FIELD(CTRL, SEC_EN, 7, 1)
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/openbmc/u-boot/arch/arm/mach-zynq/
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0+
21 .iface = devcfg,
51 writel(0x757BDF0D, &devcfg_base->unlock); in arch_cpu_init()
52 writel(0xFFFFFFFF, &devcfg_base->rom_shadow); in arch_cpu_init()
56 writel(0, &scu_base->filter_start); in arch_cpu_init()
59 writel(0x1F, &slcr_base->ocm_cfg); in arch_cpu_init()
61 writel(0x0, &slcr_base->fpga_rst_ctrl); in arch_cpu_init()
63 writel(0x0, &slcr_base->ddr_urgent_sel); in arch_cpu_init()
65 writel(0xC, &slcr_base->ddr_urgent); in arch_cpu_init()
75 return (readl(&devcfg_base->mctrl) & ZYNQ_SILICON_VER_MASK) in zynq_get_silicon_version()
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/openbmc/u-boot/drivers/fpga/
H A Dxilinx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012-2013, Xilinx, Michal Simek
24 /* ------------------------------------------------------------------------- */
29 xilinx_desc *desc_xilinx = desc->devdesc; in fpga_is_partial_data()
32 if (img_len >= desc_xilinx->size) in fpga_is_partial_data()
36 return 1; in fpga_is_partial_data()
53 xdesc = desc->devdesc; in fpga_loadbitstream()
56 length = (*dataptr << 8) + *(dataptr + 1); in fpga_loadbitstream()
61 length = (*dataptr << 8) + *(dataptr + 1); in fpga_loadbitstream()
69 length = (*dataptr << 8) + *(dataptr + 1); in fpga_loadbitstream()
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/openbmc/linux/drivers/fpga/
H A Dzynq-fpga.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011-2015 Xilinx Inc.
6 * FPGA Manager Driver for Xilinx Zynq, heavily based on xdevcfg driver
13 #include <linux/dma-mapping.h>
14 #include <linux/fpga/fpga-mgr.h>
106 #define DMA_SRC_LAST_TRANSFER 1
140 writel(val, priv->io_base + offset); in zynq_fpga_write()
146 return readl(priv->io_base + offset); in zynq_fpga_read()
150 readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \
166 first = priv->dma_elm == 0; in zynq_step_dma()
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/openbmc/linux/
H A Dopengrok1.0.log1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'
2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)
3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa
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