History log of /openbmc/u-boot/drivers/fpga/xilinx.c (Results 1 – 25 of 45)
Revision (<<< Hide revision tags) (Show revision tags >>>) Date Author Comments
Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12, v00.04.11, v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01, v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13, v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03, v00.02.02, v00.02.01, v2019.07, v00.02.00, v2019.04, v2018.07
# 582d97b6 01-Jun-2018 Tom Rini <trini@konsulko.com>

Merge tag 'xilinx-for-v2018.07-2' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.07 second pull

zynqmp:
- Show reset reason
- Remove emulation platform
- Update pmufw version
-

Merge tag 'xilinx-for-v2018.07-2' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.07 second pull

zynqmp:
- Show reset reason
- Remove emulation platform
- Update pmufw version
- Simplify mmc bootmode
- Remove dc2 useless configuration file
- Cleanup mini config
- Defconfig syncup
- zcu100, zcu104 and zcu111 dts fixes

xilinx:
- Use live-tree functions in some drivers
- Add support for Avnet Minized and Antminer S9

fpga:
- Add secure bitstream loading support

mmc:
- Add hs200 mode support

usb xhci:
- Header fix

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# a18d09ea 31-May-2018 Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

fpga: zynqmp: Add secure bitstream loading for ZynqMP

This patch adds support for loading secure bitstreams on ZynqMP
platforms. The secure bitstream images has to be generated using
Xilinx bootgen

fpga: zynqmp: Add secure bitstream loading for ZynqMP

This patch adds support for loading secure bitstreams on ZynqMP
platforms. The secure bitstream images has to be generated using
Xilinx bootgen tool.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

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# 83d290c5 06-May-2018 Tom Rini <trini@konsulko.com>

SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So

SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>

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Revision tags: v2018.03, v2018.01
# 90d75d2e 18-Dec-2017 Tom Rini <trini@konsulko.com>

Merge tag 'xilinx-for-v2018.01-rc2-v2' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.01-rc2-v2

fpga:
- Enable loading bitstream via fit image for !xilinx platforms

zynq:
- Fi

Merge tag 'xilinx-for-v2018.01-rc2-v2' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.01-rc2-v2

fpga:
- Enable loading bitstream via fit image for !xilinx platforms

zynq:
- Fix SPL SD boot mode

zynqmp:
- Not not reset in panic
- Do not use simple allocator because of fat changes
- Various dt chagnes
- modeboot variable setup
- Fix fpga loading on automotive devices
- Fix coverity issues

test:
- Fix env test for !hush case - Stephen's patch

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Revision tags: v2017.11
# 8b93a92f 10-Nov-2017 Goldschmidt Simon <sgoldschmidt@de.pepperl-fuchs.com>

fpga: allow programming fpga from FIT image for all FPGA drivers

This drops the limit that fpga is only loaded from FIT images for Xilinx.
This is done by moving the 'partial' check from 'common/ima

fpga: allow programming fpga from FIT image for all FPGA drivers

This drops the limit that fpga is only loaded from FIT images for Xilinx.
This is done by moving the 'partial' check from 'common/image.c' to
'drivers/fpga/xilinx.c' (the only driver supporting partial images yet)
and supplies a weak default implementation in 'drivers/fpga/fpga.c'.

Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Tested-by: Michal Simek <michal.simek@xilinx.com> (On zcu102)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

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# fe84c48e 04-Aug-2017 Tom Rini <trini@konsulko.com>

Merge tag 'xilinx-for-v2017.09' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2017.09

Zynq:
- Add Z-Turn board support

fpga:
- Remove intermediate buffer from code

Zynqmp:
- dts

Merge tag 'xilinx-for-v2017.09' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2017.09

Zynq:
- Add Z-Turn board support

fpga:
- Remove intermediate buffer from code

Zynqmp:
- dts cleanup
- change psu_init handling
- Add options to get silicon version
- Fix time handling
- Map OCM/TCM via MMU
- Add new clock driver

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# d863909f 02-Mar-2017 Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

fpga: xilinx: Avoid using local intermediate buffer

Dont use local temporary buffer for printing out the
info instead use directly from memroy. This fixes the
issue of stack corruprion due to local

fpga: xilinx: Avoid using local intermediate buffer

Dont use local temporary buffer for printing out the
info instead use directly from memroy. This fixes the
issue of stack corruprion due to local buffer overflow.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

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# 58c8c096 22-Sep-2016 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze


Revision tags: v2016.07, openbmc-20160624-1
# 6b245014 13-Jan-2016 Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP

Add PL bitstream dowload support for ZynqMP
Bitstream will be validated by uboot and loaded
to PL by invoking an smc instruction to

fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP

Add PL bitstream dowload support for ZynqMP
Bitstream will be validated by uboot and loaded
to PL by invoking an smc instruction to ATF which route this request to
PMU FW which will take care of loading it to PL

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

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# 19bde031 27-Jan-2016 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze


# f7213267 11-Jan-2016 Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

fpga: xilinx: Check for substring in device ID validation

Check for substrings in deviceID validation check
so that it can support xa bitstreams also.

Signed-off-by: Siva Durga Prasad Paladugu <siv

fpga: xilinx: Check for substring in device ID validation

Check for substrings in deviceID validation check
so that it can support xa bitstreams also.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

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Revision tags: v2016.01-rc1, v2015.10, v2015.10-rc5, v2015.10-rc4, v2015.10-rc3, v2015.10-rc2, v2015.10-rc1, v2015.07, v2015.07-rc3, v2015.07-rc2, v2015.07-rc1, v2015.04, v2015.04-rc5, v2015.04-rc4, v2015.04-rc3, v2015.04-rc2
# e72d3443 13-Feb-2015 Stefano Babic <sbabic@denx.de>

Merge branch 'master' of git://git.denx.de/u-boot


Revision tags: v2015.04-rc1
# 4608f379 22-Jan-2015 Tom Rini <trini@ti.com>

Merge branch 'fpga' of git://www.denx.de/git/u-boot-microblaze


Revision tags: v2015.01, v2015.01-rc4, v2015.01-rc3, v2015.01-rc2, v2015.01-rc1, v2014.10, v2014.10-rc3, v2014.10-rc2, v2014.10-rc1
# e136eaeb 16-Jul-2014 Michal Simek <michal.simek@xilinx.com>

fpga: xilinx: Show fpga info if defined

Show fpga_op->info even if desc->iface_fns is not defined.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>


# 6cd68c81 16-Jul-2014 Michal Simek <michal.simek@xilinx.com>

fpga: xilinx: Check if fpga operations are defined

Ensure that operations are correctly setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>


# dab5e346 16-Jul-2014 Stefano Babic <sbabic@denx.de>

Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>

Conflicts:
boards.cfg


Revision tags: v2014.07, v2014.07-rc4
# ed1d98d8 25-Jun-2014 Albert ARIBAUD <albert.u.boot@aribaud.net>

Merge branch 'u-boot/master' into 'u-boot-arm/master'


Revision tags: v2014.07-rc3
# ddc94378 07-Jun-2014 Simon Glass <sjg@chromium.org>

m68k: Fix warnings with gcc 4.6

Most of the warnings seem to be related to using 'int' for size_t. Change
this and fix up the remaining warnings and problems. For bootm, the warning
was masked by ot

m68k: Fix warnings with gcc 4.6

Most of the warnings seem to be related to using 'int' for size_t. Change
this and fix up the remaining warnings and problems. For bootm, the warning
was masked by others, and there is an actual bug in the code.

Signed-off-by: Simon Glass <sjg@chromium.org>

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Revision tags: v2014.07-rc2
# 4d16f67e 22-May-2014 Tom Rini <trini@ti.com>

Merge branch 'fpga' of git://www.denx.de/git/u-boot-microblaze


Revision tags: v2014.07-rc1, v2014.04, v2014.04-rc3
# 1a897668 14-Mar-2014 Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

fpga: Added support to load bit stream from SD/MMC

Added support to load a bitstream image in chunks by reading it in
chunks from SD/MMC.
Command format:
loadfs [dev] [address] [image size] [blocksi

fpga: Added support to load bit stream from SD/MMC

Added support to load a bitstream image in chunks by reading it in
chunks from SD/MMC.
Command format:
loadfs [dev] [address] [image size] [blocksize] <interface>
[<dev[:part]>] <filename>
Example: fpga loadfs 0 1000000 3dbafc 4000 mmc 0 fpga.bin

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

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# 7a78bd26 02-May-2014 Michal Simek <michal.simek@xilinx.com>

fpga: Define bitstream type based on command selection

Clean up partial, full and compressed bitstream handling.
U-Boot supports full bitstream loading and partial
based on detection which is not 10

fpga: Define bitstream type based on command selection

Clean up partial, full and compressed bitstream handling.
U-Boot supports full bitstream loading and partial
based on detection which is not 100% correct.
Extending fpga_load/fpga_loadbitstream() with one more
argument which stores bitstream type.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

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# 05d134b0 20-May-2014 Albert ARIBAUD <albert.u.boot@aribaud.net>

Merge remote-tracking branch 'u-boot/master'

Conflicts:
boards.cfg

Conflicts were trivial once u-boot-arm/master boards.cfg was
reformatted (commit 6130c146) to match u-boot/master's own
reformatt

Merge remote-tracking branch 'u-boot/master'

Conflicts:
boards.cfg

Conflicts were trivial once u-boot-arm/master boards.cfg was
reformatted (commit 6130c146) to match u-boot/master's own
reformatting (commit 1b37fa83).

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# 4180b3db 14-May-2014 Marek Vasut <marex@denx.de>

Merge remote-tracking branch 'u-boot/master' into test


# 27b4e4b9 13-May-2014 Tom Rini <trini@ti.com>

Merge branch 'fpga' of git://www.denx.de/git/u-boot-microblaze


# 14cfc4f3 13-Mar-2014 Michal Simek <michal.simek@xilinx.com>

fpga: xilinx: Simplify load/dump/info function handling

Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2

fpga: xilinx: Simplify load/dump/info function handling

Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

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