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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Drohm,bd9576-pmic.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rohm,bd9576-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
14 powering the R-Car series processors.
16 monitoring. A watchdog logic with slow ping/windowed modes is also included.
21 - rohm,bd9576
22 - rohm,bd9573
32 rohm,vout1-en-low:
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/openbmc/u-boot/lib/efi_selftest/
H A Defi_selftest_watchdog.c1 // SPDX-License-Identifier: GPL-2.0+
7 * The 'watchdog timer' unit test checks that the watchdog timer
8 * will not cause a system restart during the timeout period after
11 * The 'watchdog reboot' unit test checks that the watchdog timer
12 * actually reboots the system after a timeout. The test is only
15 * setenv efi_selftest watchdog reboot
25 /* Status code returned when resetting watchdog */
42 * @context pointer to the timeout
52 /* Reset watchdog timer to one second */ in notify()
53 ret = boottime->set_watchdog_timer(1, 0, 0, NULL); in notify()
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/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dziirave-wdt.txt1 Zodiac RAVE Watchdog Timer
4 - compatible: must be "zii,rave-wdt"
5 - reg: i2c slave address of device, usually 0x38
8 - timeout-sec: Watchdog timeout value in seconds.
9 - reset-duration-ms: Duration of the pulse generated when the watchdog times
14 watchdog@38 {
15 compatible = "zii,rave-wdt";
17 timeout-sec = <30>;
18 reset-duration-ms = <30>;
H A Dcdns,wdt-r1p2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/cdns,wdt-r1p2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence watchdog timer controller
10 - Neeli Srinivas <srinivas.neeli@amd.com>
13 The cadence watchdog timer is used to detect and recover from
14 system malfunctions. This watchdog contains 24 bit counter and
15 a programmable reset period. The timeout period varies from 1 ms
19 - $ref: watchdog.yaml#
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H A Dnuvoton,npcm-wdt.txt1 Nuvoton NPCM Watchdog
3 Nuvoton NPCM timer module provides five 24-bit timer counters, and a watchdog.
4 The watchdog supports a pre-timeout interrupt that fires 10ms before the
8 - compatible : "nuvoton,npcm750-wdt" for NPCM750 (Poleg), or
9 "nuvoton,wpcm450-wdt" for WPCM450 (Hermon), or
10 "nuvoton,npcm845-wdt" for NPCM845 (Arbel).
11 - reg : Offset and length of the register set for the device.
12 - interrupts : Contain the timer interrupt with flags for
16 - clocks : phandle of timer reference clock.
17 - clock-frequency : The frequency in Hz of the clock that drives the NPCM7xx
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/openbmc/linux/drivers/watchdog/
H A Dsc520_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AMD Elan SC520 processor Watchdog Timer driver
9 * any of this software. This material is provided "AS-IS" in
13 * 9/27 - 2001 [Initial release]
16 * - Fixed formatting
17 * - Removed debug printks
18 * - Fixed SMP built kernel deadlock
19 * - Switched to private locks not lock_kernel
20 * - Used ioremap/writew/readw
21 * - Added NOWAYOUT support
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H A Dshwdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/watchdog/shwdt.c
5 * Watchdog driver for integrated watchdog in the SuperH processors.
7 * Copyright (C) 2001 - 2012 Paul Mundt <lethal@linux-sh.org>
9 * 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
12 * 19-Apr-2002 Rob Radez <rob@osinvestor.com>
13 * Added expect close support, made emulated timeout runtime changeable
25 #include <linux/watchdog.h>
33 #include <asm/watchdog.h>
35 #define DRV_NAME "sh-wdt"
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H A Drave-sp-wdt.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Driver for watchdog aspect of for Zodiac Inflight Innovations RAVE
13 #include <linux/mfd/rave-sp.h>
15 #include <linux/nvmem-consumer.h>
20 #include <linux/watchdog.h>
29 * struct rave_sp_wdt_variant - RAVE SP watchdog variant
31 * @max_timeout: Largest possible watchdog timeout setting
32 * @min_timeout: Smallest possible watchdog timeout setting
46 * struct rave_sp_wdt - RAVE SP watchdog
48 * @wdd: Underlying watchdog device
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H A Dimx_sc_wdt.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2018-2019 NXP.
6 #include <linux/arm-smccc.h>
14 #include <linux/watchdog.h>
18 * Software timer tick implemented in scfw side, support 10ms to 0xffffffff ms
40 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
65 return -EACCES; in imx_sc_wdt_start()
70 return res.a0 ? -EACCES : 0; in imx_sc_wdt_start()
80 return res.a0 ? -EACCES : 0; in imx_sc_wdt_stop()
84 unsigned int timeout) in imx_sc_wdt_set_timeout() argument
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H A Dsun4v_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sun4v watchdog timer
6 * Implement a simple watchdog driver using the built-in sun4v hypervisor
7 * watchdog support. If time expires, the hypervisor stops or bounces
18 #include <linux/watchdog.h>
27 static unsigned int timeout; variable
28 module_param(timeout, uint, 0);
29 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
34 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
49 * HV watchdog timer will round up the timeout in sun4v_wdt_ping()
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H A Dadvantech_ec_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Advantech Embedded Controller Watchdog Driver
17 #include <linux/watchdog.h>
25 /* EC minimum IO access delay in ms */
47 static unsigned int timeout; variable
50 module_param(timeout, uint, 0);
51 MODULE_PARM_DESC(timeout,
52 …"Default Watchdog timer setting (" __MODULE_STRING(DEFAULT_TIME) "s). The range is from " __MODULE…
62 time_delta = EC_MIN_DELAY - time_delta; in adv_ec_wdt_timing_gate()
90 /* scale time to EC 100 ms base */ in adv_ec_wdt_set_timeout()
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H A Dpnx4008_wdt.c1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/char/watchdog/pnx4008_wdt.c
5 * Watchdog driver for PNX4008 board
12 * 2005-2006 (c) MontaVista Software, Inc.
23 #include <linux/watchdog.h>
34 /* WatchDog Timer - Chapter 23 Page 207 */
39 /* Watchdog timer register set definition */
98 /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */ in pnx4008_wdt_start()
100 writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base)); in pnx4008_wdt_start()
121 wdd->timeout = new_timeout; in pnx4008_wdt_set_timeout()
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H A Dbd9576_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * ROHM BD9576MUF and BD9573MUF Watchdog driver
10 #include <linux/mfd/rohm-bd957x.h>
15 #include <linux/watchdog.h>
20 "Watchdog cannot be stopped once started (default=\"false\")");
37 gpiod_set_value_cansleep(priv->gpiod_en, 0); in bd9576_wdt_disable()
45 gpiod_set_value_cansleep(priv->gpiod_ping, 1); in bd9576_wdt_ping()
46 gpiod_set_value_cansleep(priv->gpiod_ping, 0); in bd9576_wdt_ping()
55 gpiod_set_value_cansleep(priv->gpiod_en, 1); in bd9576_wdt_start()
72 .identity = "BD957x Watchdog",
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H A Dts4800_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Watchdog driver for TS-4800 based boards
5 * Copyright (c) 2015 - Savoir-faire Linux
15 #include <linux/watchdog.h>
20 "Watchdog cannot be stopped once started (default="
36 * TS-4800 supports the following timeout values:
39 * ---------------------
40 * 0 feed for 338ms
43 * 3 disable watchdog
45 * Keep the regmap/timeout map ordered by timeout
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H A Dda9063_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Watchdog driver for DA9063 PMICs.
13 #include <linux/watchdog.h>
25 * Watchdog selector to timeout in seconds.
27 * others: timeout = 2048 ms * 2^(TWDSCALE-1).
34 #define DA9063_TWDSCALE_MAX (ARRAY_SIZE(wdt_timeout) - 1)
53 * Read the currently active timeout.
54 * Zero means the watchdog is disabled.
60 regmap_read(da9063->regmap, DA9063_REG_CONTROL_D, &val); in da9063_wdt_read_timeout()
67 return regmap_update_bits(da9063->regmap, DA9063_REG_CONTROL_D, in da9063_wdt_disable_timer()
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H A Dmenf21bmc_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MEN 14F021P00 Board Management Controller (BMC) Watchdog Driver.
11 #include <linux/watchdog.h>
30 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
42 rst_rsn = i2c_smbus_read_byte_data(data->i2c_client, BMC_CMD_RST_RSN); in menf21bmc_wdt_set_bootstatus()
47 data->wdt.bootstatus |= WDIOF_CARDRESET; in menf21bmc_wdt_set_bootstatus()
49 data->wdt.bootstatus |= WDIOF_EXTERN1; in menf21bmc_wdt_set_bootstatus()
51 data->wdt.bootstatus |= WDIOF_EXTERN2; in menf21bmc_wdt_set_bootstatus()
53 data->wdt.bootstatus |= WDIOF_POWERUNDER; in menf21bmc_wdt_set_bootstatus()
62 return i2c_smbus_write_byte(drv_data->i2c_client, BMC_CMD_WD_ON); in menf21bmc_wdt_start()
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H A Ddb8500_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2011-2013
5 * Author: Mathieu Poirier <mathieu.poirier@linaro.org> for ST-Ericsson
6 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
16 #include <linux/watchdog.h>
19 #include <linux/mfd/dbx500-prcmu.h>
24 #define WATCHDOG_MAX28 268435 /* 28 bit resolution in ms == 268435.455 s */
26 static unsigned int timeout = WATCHDOG_TIMEOUT; variable
27 module_param(timeout, uint, 0);
28 MODULE_PARM_DESC(timeout,
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H A Dapple_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Apple SoC Watchdog driver
17 #include <linux/watchdog.h>
20 * Apple Watchdog MMIO registers
71 writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME); in apple_wdt_start()
72 writel_relaxed(APPLE_WDT_CTRL_RESET_EN, wdt->regs + APPLE_WDT_WD1_CTRL); in apple_wdt_start()
81 writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CTRL); in apple_wdt_stop()
90 writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME); in apple_wdt_ping()
99 writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME); in apple_wdt_set_timeout()
100 writel_relaxed(wdt->clk_rate * s, wdt->regs + APPLE_WDT_WD1_BITE_TIME); in apple_wdt_set_timeout()
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H A Dvia_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * VIA Chipset Watchdog Driver
10 * Caveat: PnP must be enabled in BIOS to allow full access to watchdog
11 * control registers. If not, the watchdog must be configured in BIOS manually.
22 #include <linux/watchdog.h>
26 #define VIA_WDT_CONF 0xec /* watchdog enable state */
29 #define VIA_WDT_CONF_ENABLE 0x01 /* 1: enable watchdog */
30 #define VIA_WDT_CONF_MMIO 0x02 /* 1: enable watchdog MMIO */
33 * The MMIO region contains the watchdog control register and the
42 #define VIA_WDT_FIRED 0x02 /* 1: restarted by expired watchdog */
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/openbmc/u-boot/arch/arm/mach-at91/
H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2008
19 #include <watchdog.h>
25 unsigned long const timeout = 1000; /* 1000ms */ in at91_phy_reset() local
28 erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; in at91_phy_reset()
31 * Need to reset PHY -> 500ms reset in at91_phy_reset()
32 * Reset PHY by pulling the NRST line for 500ms to low. To do so in at91_phy_reset()
37 AT91_RSTC_MR_URSTEN, &rstc->mr); in at91_phy_reset()
39 writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); in at91_phy_reset()
42 while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) { in at91_phy_reset()
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/openbmc/linux/Documentation/devicetree/bindings/power/supply/
H A Dbq256xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Davis <afd@ti.com>
14 The bq256xx devices are a family of highly-integrated battery charge
15 management and system power management ICs for single cell Li-ion and Li-
19 - https://www.ti.com/lit/ds/symlink/bq25600.pdf
20 - https://www.ti.com/lit/ds/symlink/bq25601.pdf
21 - https://www.ti.com/lit/ds/symlink/bq25600d.pdf
22 - https://www.ti.com/lit/ds/symlink/bq25601d.pdf
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H A Dbq25980.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Davis <afd@ti.com>
15 for use in high-power density portable electronics. These inductorless
20 - $ref: power-supply.yaml#
25 - ti,bq25980
26 - ti,bq25975
27 - ti,bq25960
32 ti,watchdog-timeout-ms:
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/openbmc/openbmc-test-automation/ipmi/
H A Dtest_ipmi_watchdog.robot3 Documentation Module to test out of band IPMI watchdog functionality.
21 Test IPMI Watchdog Timer Does Not Log Bit
22 [Documentation] Execute out of band set/get do not log bit for watchdog timer.
27 ${IPMI_RAW_CMD['Watchdog']['Set'][0]} ${IPMI_RAW_CMD['Watchdog']['Get'][0]}
28 ... ${IPMI_RAW_CMD['Watchdog']['Get'][1]}
29 ${IPMI_RAW_CMD['Watchdog']['Set'][3]} ${IPMI_RAW_CMD['Watchdog']['Get'][0]}
30 ... ${IPMI_RAW_CMD['Watchdog']['Get'][3]}
32 Test IPMI Watchdog Timer Stop Bit
33 [Documentation] Execute out of band set/get stop/resume timer stop bit for watchdog timer.
35 [Template] Execute IPMI Raw Command And Verify Response Data After Watchdog Expires
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/openbmc/linux/drivers/comedi/drivers/
H A Daddi_watchdog.c1 // SPDX-License-Identifier: GPL-2.0+
3 * COMEDI driver for the watchdog subdevice found on some addi-data boards
6 * Based on implementations in various addi-data COMEDI drivers.
8 * COMEDI - Linux Control and Measurement Device Interface
23 * The watchdog subdevice is configured with two INSN_CONFIG instructions:
25 * Enable the watchdog and set the reload timeout:
27 * data[1] = timeout reload value
29 * Disable the watchdog:
37 struct addi_watchdog_private *spriv = s->private; in addi_watchdog_insn_config()
42 spriv->wdog_ctrl = ADDI_TCW_CTRL_ENA; in addi_watchdog_insn_config()
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/openbmc/u-boot/drivers/watchdog/
H A Darmada-37xx-wdt.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell Armada 37xx SoC Watchdog Driver
21 u64 timeout; member
25 * We use Counter 1 as watchdog timer, and Counter 0 for re-triggering Counter 1
45 writel(val & 0xffffffff, priv->reg + CNTR_COUNT_LOW(id)); in set_counter_value()
46 writel(val >> 32, priv->reg + CNTR_COUNT_HIGH(id)); in set_counter_value()
51 setbits_le32(priv->reg + CNTR_CTRL(id), CNTR_CTRL_ENABLE); in counter_enable()
56 clrbits_le32(priv->reg + CNTR_CTRL(id), CNTR_CTRL_ENABLE); in counter_disable()
63 reg = readl(priv->reg + CNTR_CTRL(id)); in init_counter()
65 return -EBUSY; in init_counter()
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