/openbmc/linux/Documentation/devicetree/bindings/display/ti/ |
H A D | ti,j721e-dss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Jyri Sarha <jsarha@ti.com> 12 - Tomi Valkeinen <tomi.valkeinen@ti.com> 15 The J721E TI Keystone Display SubSystem with four output ports and 16 four video planes. There is two full video planes and two "lite 17 planes" without scaling support. The video ports can be connected to 22 const: ti,j721e-dss [all …]
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H A D | ti,am65x-dss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Jyri Sarha <jsarha@ti.com> 12 - Tomi Valkeinen <tomi.valkeinen@ti.com> 16 ports and two video planes. In AM65x DSS, the first video port 17 supports 1 OLDI TX and in AM625 DSS, the first video port output is 18 internally routed to 2 OLDI TXes. The second video port supports DPI 19 format. The first plane is full video plane with all features and the [all …]
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H A D | ti,omap-dss.txt | 5 ------------------- 21 The encoder modules encode the received RGB pixel stream to a video output like 24 Video Ports 25 ----------- 27 The DSS Core and the encoders have video port outputs. The structure of the 28 video ports is described in Documentation/devicetree/bindings/graph.txt, 29 and the properties for the ports and endpoints for each encoder are 32 The video ports are used to describe the connections to external hardware, like 36 ------- 39 name for each display. If no aliases are defined, a semi-random number is used [all …]
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/openbmc/linux/Documentation/devicetree/bindings/media/ |
H A D | video-mux.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/media/video-mux.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Video Multiplexer 10 - Sakari Ailus <sakari.ailus@linux.intel.com> 11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 14 Video multiplexers allow to select between multiple input ports. Video 20 const: video-mux 22 mux-controls: [all …]
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H A D | imx.txt | 1 Freescale i.MX Media Video Device 4 Video Media Controller node 5 --------------------------- 7 This is the media controller node for video capture support. It is a 12 - compatible : "fsl,imx-capture-subsystem"; 13 - ports : Should contain a list of phandles pointing to camera 14 sensor interface ports of IPU devices 18 capture-subsystem { 19 compatible = "fsl,imx-capture-subsystem"; 20 ports = <&ipu1_csi0>, <&ipu1_csi1>; [all …]
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H A D | microchip,csi2dc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Eugen Hristev <eugen.hristev@microchip.com> 13 CSI2DC - Camera Serial Interface 2 Demux Controller 25 CSI2DC provides two pipes, one video pipe and one data pipe. Video pipe 30 32-bit IDI interface or a parallel interface. 33 This is called video pipe. 44 const: microchip,sama7g5-csi2dc 53 clock-names: [all …]
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H A D | renesas,rzg2l-csi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/media/renesas,rzg2l-csi2.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Renesas RZ/G2L (and alike SoC's) MIPI CSI-2 receiver 11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 14 The CSI-2 receiver device provides MIPI CSI-2 capabilities for the Renesas RZ/G2L 15 (and alike SoCs). MIPI CSI-2 is part of the CRU block which is used in conjunction 16 with the Image Processing module, which provides the video capture capabilities. 21 - enum: [all …]
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/openbmc/linux/Documentation/devicetree/bindings/display/bridge/ |
H A D | ti,sn65dsi83.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Marek Vasut <marex@denx.de> 13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI 14 to 1x Single-link LVDS 16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI 17 to 1x Dual-link or 2x Single-link LVDS 23 - ti,sn65dsi83 24 - ti,sn65dsi84 [all …]
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H A D | nxp,tda998x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Russell King <linux@armlinux.org.uk> 22 video-ports: 27 24 bits value which defines how the video controller output is wired to 30 audio-ports: 32 Array of 8-bit values, 2 values per DAI (Documentation/sound/soc/dai.rst). 35 $ref: /schemas/types.yaml#/definitions/uint32-matrix 39 - description: | [all …]
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H A D | megachips-stdpxxxx-ge-b850v3-fw.txt | 1 Drivers for the second video output of the GE B850v3: 2 STDP4028-ge-b850v3-fw bridges (LVDS-DP) 3 STDP2690-ge-b850v3-fw bridges (DP-DP++) 5 The video processing pipeline on the second output on the GE B850v3: 7 Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output 12 suffix "-ge-b850v3-fw" to make it clear that the driver is for the bridges with 15 The hardware do not provide control over the video processing pipeline, as the 19 stdp4028-ge-b850v3-fw required properties: 20 - compatible : "megachips,stdp4028-ge-b850v3-fw" 21 - reg : I2C bus address [all …]
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H A D | ps8640.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: MIPI DSI to eDP Video Format Converter 10 - Nicolas Boichat <drinkcat@chromium.org> 13 The PS8640 is a low power MIPI-to-eDP video format converter supporting 28 powerdown-gpios: 32 reset-gpios: 36 vdd12-supply: 39 vdd33-supply: [all …]
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H A D | fsl,ldb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Marek Vasut <marex@denx.de> 14 for configuring the on-SoC DPI-to-LVDS serializer. This describes 20 - fsl,imx6sx-ldb 21 - fsl,imx8mp-ldb 22 - fsl,imx93-ldb 27 clock-names: 33 reg-names: [all …]
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H A D | adi,adv7533.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 13 The ADV7533 and ADV7535 are HDMI audio and video transmitters 20 - adi,adv7533 21 - adi,adv7535 35 reg-names: 38 needing a non-default address. 41 - const: main [all …]
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H A D | adi,adv7511.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 13 The ADV7511, ADV7511W and ADV7513 are HDMI audio and video 21 - adi,adv7511 22 - adi,adv7511w 23 - adi,adv7513 37 reg-names: 40 needing a non-default address. [all …]
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H A D | chipone,icn6211.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge 10 - Jagan Teki <jagan@amarulasolutions.com> 13 ICN6211 is MIPI-DSI to RGB Converter bridge from chipone. 21 - chipone,icn6211 27 clock-names: 36 enable-gpios: 39 vdd1-supply: [all …]
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/openbmc/linux/Documentation/devicetree/bindings/media/i2c/ |
H A D | adv7180.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Analog Devices ADV7180 analog video decoder family 10 - Lars-Peter Clausen <lars@metafoo.de> 13 The adv7180 family devices are used to capture analog video to different 14 digital interfaces like MIPI CSI-2 or parallel video. 19 - enum: 20 - adi,adv7180 21 - adi,adv7180cp [all …]
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H A D | st,st-mipid02.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/media/i2c/st,st-mipid02.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge 10 - Benjamin Mugnier <benjamin.mugnier@foss.st.com> 11 - Sylvain Petinot <sylvain.petinot@foss.st.com> 14 MIPID02 has two CSI-2 input ports, only one of those ports can be 15 active at a time. Active port input stream will be de-serialized 17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 [all …]
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H A D | adv748x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Analog Devices ADV748X video decoder with HDMI receiver 10 - Kieran Bingham <kieran.bingham@ideasonboard.com> 11 - Niklas Söderlund <niklas.soderlund@ragnatech.se> 14 The ADV7481 and ADV7482 are multi format video decoders with an integrated 15 HDMI receiver. They can output CSI-2 on two independent outputs TXA and TXB 21 - enum: 22 - adi,adv7481 [all …]
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H A D | ti,ds90ub913.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Texas Instruments DS90UB913 FPD-Link III Serializer 10 - Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> 13 The TI DS90UB913 is an FPD-Link III video serializer for parallel video. 18 - ti,ds90ub913a-q1 20 '#gpio-cells': 27 gpio-controller: true 34 clock-names: [all …]
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/openbmc/linux/Documentation/devicetree/bindings/media/xilinx/ |
H A D | xlnx,video.txt | 1 Xilinx Video IP Pipeline (VIPP) 2 ------------------------------- 5 --------------- 7 Xilinx video IP pipeline processes video streams through one or more Xilinx 8 video IP cores. Each video IP core is represented as documented in video.txt 9 and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT 11 mappings between DMAs and the video IP cores. 15 - compatible: Must be "xlnx,video". 17 - dmas, dma-names: List of one DMA specifier and identifier string (as defined 22 - ports: Video port, using the DT bindings defined in ../video-interfaces.txt. [all …]
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H A D | xlnx,csi2rxss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Xilinx MIPI CSI-2 Receiver Subsystem 10 - Vishal Sagar <vishal.sagar@amd.com> 13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2 15 video data for image processing. 16 The subsystem consists of a MIPI D-PHY in slave mode which captures the 17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the 18 packet data. The optional Video Format Bridge (VFB) converts this data to [all …]
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H A D | xlnx,v-tpg.txt | 1 Xilinx Video Test Pattern Generator (TPG) 2 ----------------------------------------- 6 - compatible: Must contain at least one of 8 "xlnx,v-tpg-5.0" (TPG version 5.0) 9 "xlnx,v-tpg-6.0" (TPG version 6.0) 11 TPG versions backward-compatible with previous versions should list all 14 - reg: Physical base address and length of the registers set for the device. 16 - clocks: Reference to the video core clock. 18 - xlnx,video-format, xlnx,video-width: Video format and width, as defined in 19 video.txt. [all …]
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/openbmc/linux/Documentation/devicetree/bindings/display/xlnx/ |
H A D | xlnx,zynqmp-dpsub.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 14 +------------------------------------------------------------+ 15 +--------+ | +----------------+ +-----------+ | 16 | DPDMA | --->| | --> | Video | Video +-------------+ | 17 | 4x vid | | | | | Rendering | -+--> | | | +------+ 18 | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 | 19 +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+ [all …]
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/openbmc/linux/Documentation/devicetree/bindings/display/tegra/ |
H A D | nvidia,tegra20-vip.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vip.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra VIP (parallel video capture) controller 10 - Luca Ceresoli <luca.ceresoli@bootlin.com> 15 - nvidia,tegra20-vip 17 ports: 18 $ref: /schemas/graph.yaml#/properties/ports 24 Port receiving the video stream from the sensor [all …]
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/openbmc/linux/Documentation/devicetree/bindings/display/rockchip/ |
H A D | rockchip-vop2.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 VOP2 (Video Output Processor v2) is the display controller for the Rockchip 11 series of SoCs which transfers the image data from a video memory 15 - Sandy Huang <hjc@rock-chips.com> 16 - Heiko Stuebner <heiko@sntech.de> 21 - rockchip,rk3566-vop 22 - rockchip,rk3568-vop [all …]
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