1*b2fdab37SPeter Senna TschudinDrivers for the second video output of the GE B850v3: 2*b2fdab37SPeter Senna Tschudin STDP4028-ge-b850v3-fw bridges (LVDS-DP) 3*b2fdab37SPeter Senna Tschudin STDP2690-ge-b850v3-fw bridges (DP-DP++) 4*b2fdab37SPeter Senna Tschudin 5*b2fdab37SPeter Senna TschudinThe video processing pipeline on the second output on the GE B850v3: 6*b2fdab37SPeter Senna Tschudin 7*b2fdab37SPeter Senna Tschudin Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output 8*b2fdab37SPeter Senna Tschudin 9*b2fdab37SPeter Senna TschudinEach bridge has a dedicated flash containing firmware for supporting the custom 10*b2fdab37SPeter Senna Tschudindesign. The result is that, in this design, neither the STDP4028 nor the 11*b2fdab37SPeter Senna TschudinSTDP2690 behave as the stock bridges would. The compatible strings include the 12*b2fdab37SPeter Senna Tschudinsuffix "-ge-b850v3-fw" to make it clear that the driver is for the bridges with 13*b2fdab37SPeter Senna Tschudinthe firmware specific for the GE B850v3. 14*b2fdab37SPeter Senna Tschudin 15*b2fdab37SPeter Senna TschudinThe hardware do not provide control over the video processing pipeline, as the 16*b2fdab37SPeter Senna Tschudintwo bridges behaves as a single one. The only interfaces exposed by the 17*b2fdab37SPeter Senna Tschudinhardware are EDID, HPD, and interrupts. 18*b2fdab37SPeter Senna Tschudin 19*b2fdab37SPeter Senna Tschudinstdp4028-ge-b850v3-fw required properties: 20*b2fdab37SPeter Senna Tschudin - compatible : "megachips,stdp4028-ge-b850v3-fw" 21*b2fdab37SPeter Senna Tschudin - reg : I2C bus address 22*b2fdab37SPeter Senna Tschudin - interrupts : one interrupt should be described here, as in 23*b2fdab37SPeter Senna Tschudin <0 IRQ_TYPE_LEVEL_HIGH> 24*b2fdab37SPeter Senna Tschudin - ports : One input port(reg = <0>) and one output port(reg = <1>) 25*b2fdab37SPeter Senna Tschudin 26*b2fdab37SPeter Senna Tschudinstdp2690-ge-b850v3-fw required properties: 27*b2fdab37SPeter Senna Tschudin compatible : "megachips,stdp2690-ge-b850v3-fw" 28*b2fdab37SPeter Senna Tschudin - reg : I2C bus address 29*b2fdab37SPeter Senna Tschudin - ports : One input port(reg = <0>) and one output port(reg = <1>) 30*b2fdab37SPeter Senna Tschudin 31*b2fdab37SPeter Senna TschudinExample: 32*b2fdab37SPeter Senna Tschudin 33*b2fdab37SPeter Senna Tschudin&mux2_i2c2 { 34*b2fdab37SPeter Senna Tschudin clock-frequency = <100000>; 35*b2fdab37SPeter Senna Tschudin 36*b2fdab37SPeter Senna Tschudin stdp4028@73 { 37*b2fdab37SPeter Senna Tschudin compatible = "megachips,stdp4028-ge-b850v3-fw"; 38*b2fdab37SPeter Senna Tschudin #address-cells = <1>; 39*b2fdab37SPeter Senna Tschudin #size-cells = <0>; 40*b2fdab37SPeter Senna Tschudin 41*b2fdab37SPeter Senna Tschudin reg = <0x73>; 42*b2fdab37SPeter Senna Tschudin 43*b2fdab37SPeter Senna Tschudin interrupt-parent = <&gpio2>; 44*b2fdab37SPeter Senna Tschudin interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 45*b2fdab37SPeter Senna Tschudin 46*b2fdab37SPeter Senna Tschudin ports { 47*b2fdab37SPeter Senna Tschudin #address-cells = <1>; 48*b2fdab37SPeter Senna Tschudin #size-cells = <0>; 49*b2fdab37SPeter Senna Tschudin 50*b2fdab37SPeter Senna Tschudin port@0 { 51*b2fdab37SPeter Senna Tschudin reg = <0>; 52*b2fdab37SPeter Senna Tschudin stdp4028_in: endpoint { 53*b2fdab37SPeter Senna Tschudin remote-endpoint = <&lvds0_out>; 54*b2fdab37SPeter Senna Tschudin }; 55*b2fdab37SPeter Senna Tschudin }; 56*b2fdab37SPeter Senna Tschudin port@1 { 57*b2fdab37SPeter Senna Tschudin reg = <1>; 58*b2fdab37SPeter Senna Tschudin stdp4028_out: endpoint { 59*b2fdab37SPeter Senna Tschudin remote-endpoint = <&stdp2690_in>; 60*b2fdab37SPeter Senna Tschudin }; 61*b2fdab37SPeter Senna Tschudin }; 62*b2fdab37SPeter Senna Tschudin }; 63*b2fdab37SPeter Senna Tschudin }; 64*b2fdab37SPeter Senna Tschudin 65*b2fdab37SPeter Senna Tschudin stdp2690@72 { 66*b2fdab37SPeter Senna Tschudin compatible = "megachips,stdp2690-ge-b850v3-fw"; 67*b2fdab37SPeter Senna Tschudin #address-cells = <1>; 68*b2fdab37SPeter Senna Tschudin #size-cells = <0>; 69*b2fdab37SPeter Senna Tschudin 70*b2fdab37SPeter Senna Tschudin reg = <0x72>; 71*b2fdab37SPeter Senna Tschudin 72*b2fdab37SPeter Senna Tschudin ports { 73*b2fdab37SPeter Senna Tschudin #address-cells = <1>; 74*b2fdab37SPeter Senna Tschudin #size-cells = <0>; 75*b2fdab37SPeter Senna Tschudin 76*b2fdab37SPeter Senna Tschudin port@0 { 77*b2fdab37SPeter Senna Tschudin reg = <0>; 78*b2fdab37SPeter Senna Tschudin stdp2690_in: endpoint { 79*b2fdab37SPeter Senna Tschudin remote-endpoint = <&stdp4028_out>; 80*b2fdab37SPeter Senna Tschudin }; 81*b2fdab37SPeter Senna Tschudin }; 82*b2fdab37SPeter Senna Tschudin 83*b2fdab37SPeter Senna Tschudin port@1 { 84*b2fdab37SPeter Senna Tschudin reg = <1>; 85*b2fdab37SPeter Senna Tschudin stdp2690_out: endpoint { 86*b2fdab37SPeter Senna Tschudin /* Connector for external display */ 87*b2fdab37SPeter Senna Tschudin }; 88*b2fdab37SPeter Senna Tschudin }; 89*b2fdab37SPeter Senna Tschudin }; 90*b2fdab37SPeter Senna Tschudin }; 91*b2fdab37SPeter Senna Tschudin}; 92