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/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dnand-chip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: mtd.yaml#
18 SPI-NAND devices are concerned by this description.
23 Contains the chip-select IDs.
25 nand-ecc-engine:
27 A phandle on the hardware ECC engine if any. There are
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H A Dgpmi-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale General-Purpose Media Interface (GPMI)
10 - Han Xu <han.xu@nxp.com>
14 flash chips. The device tree may optionally contain sub-nodes
21 - enum:
22 - fsl,imx23-gpmi-nand
23 - fsl,imx28-gpmi-nand
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/openbmc/u-boot/drivers/mtd/nand/raw/
H A DKconfig9 This option, if enabled, provides more flexible and linux-like
15 Omit standard ECC layouts to safe space. Select this if your driver
16 is known to provide its own ECC layout.
28 bool "Atmel Hardware ECC"
32 bool "Atmel Programmable Multibit ECC (PMECC)"
36 The Programmable Multibit ECC (PMECC) controller is a programmable
40 int "PMECC Correctable ECC Bits"
44 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
59 Generate Programmable Multibit ECC (PMECC) header for SPL image.
88 of OOB area before last ECC sector data starts. This is potentially
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H A Dmxs_nand_dt.c10 * SPDX-License-Identifier: GPL-2.0+
34 .compatible = "fsl,imx6q-gpmi-nand",
38 .compatible = "fsl,imx7d-gpmi-nand",
53 info->max_ecc_strength_supported = data->max_ecc_strength_supported; in mxs_nand_dt_probe()
55 info->dev = dev; in mxs_nand_dt_probe()
57 ret = dev_read_resource_byname(dev, "gpmi-nand", &res); in mxs_nand_dt_probe()
61 info->gpmi_regs = devm_ioremap(dev, res.start, resource_size(&res)); in mxs_nand_dt_probe()
68 info->bch_regs = devm_ioremap(dev, res.start, resource_size(&res)); in mxs_nand_dt_probe()
70 info->use_minimum_ecc = dev_read_bool(dev, "fsl,use-minimum-ecc"); in mxs_nand_dt_probe()
76 .name = "mxs-nand-dt",
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H A Datmel_nand.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2008
9 * Add Programmable Multibit ECC support for various AT91 SoC
30 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
71 * Return number of ecc bytes per sector according to sector size and
77 * 2-bits 4-bytes 4-bytes
78 * 4-bits 7-bytes 7-bytes
79 * 8-bits 13-bytes 14-bytes
80 * 12-bits 20-bytes 21-bytes
81 * 24-bits 39-bytes 42-bytes
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H A Dnand_base.c7 * http://www.linux-mtd.infradead.org/doc/nand.html
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
113 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { in check_offs_len()
115 ret = -EINVAL; in check_offs_len()
119 if (len & ((1ULL << chip->phys_erase_shift) - 1)) { in check_offs_len()
121 ret = -EINVAL; in check_offs_len()
128 * nand_release_device - [GENERIC] release chip
137 /* De-select the NAND device */ in nand_release_device()
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/openbmc/u-boot/arch/arm/dts/
H A Dimx7-colibri-rawnand.dts1 // SPDX-License-Identifier: GPL-2.0+ OR X11
6 /dts-v1/;
7 #include "imx7-colibri.dtsi"
11 compatible = "toradex,imx7-colibri", "fsl,imx7";
14 stdout-path = &uart1;
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_gpmi_nand>;
21 fsl,use-minimum-ecc;
22 nand-on-flash-bbt;
23 nand-ecc-mode = "hw";
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/openbmc/linux/Documentation/devicetree/bindings/cache/
H A Dl2c2x0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
33 - enum:
34 - arm,pl310-cache
35 - arm,l220-cache
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/openbmc/linux/drivers/mtd/nand/raw/gpmi-nand/
H A Dgpmi-nand.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
18 #include <linux/dma/mxs-dma.h>
19 #include "gpmi-nand.h"
20 #include "gpmi-regs.h"
21 #include "bch-regs.h"
24 #define GPMI_NAND_GPMI_REGS_ADDR_RES_NAME "gpmi-nand"
52 while ((readl(addr) & mask) && --timeout) in clear_poll_bit()
96 while ((!(readl(reset_addr) & MODULE_CLKGATE)) && --timeout) in gpmi_reset_block()
116 return -ETIMEDOUT; in gpmi_reset_block()
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-myir-mys-6ulx-eval.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include "imx6ull-myir-mys-6ulx.dtsi"
12 model = "MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND";
13 compatible = "myir,imx6ull-mys-6ulx-eval", "fsl,imx6ull";
17 fsl,use-minimum-ecc;
/openbmc/linux/drivers/mtd/nand/raw/
H A Dmtk_nand.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
10 #include <linux/dma-mapping.h>
19 #include <linux/mtd/nand-ecc-mtk.h>
89 #define MTK_NAME "mtk-nand"
146 struct mtk_ecc *ecc; member
185 return (u8 *)p + i * chip->ecc.size; in data_ptr()
197 if (i < mtk_nand->bad_mark.sec) in oob_ptr()
198 poi = chip->oob_poi + (i + 1) * mtk_nand->fdm.reg_size; in oob_ptr()
199 else if (i == mtk_nand->bad_mark.sec) in oob_ptr()
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H A Ddenali.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright © 2009-2010, Intel Corporation and its suppliers.
6 * Copyright (c) 2017-2019 Socionext Inc.
12 #include <linux/dma-mapping.h>
23 #define DENALI_NAND_NAME "denali-nand"
31 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
39 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
41 #define DENALI_INVALID_BANK -1
50 return container_of(chip->controller, struct denali_controller, in to_denali_controller()
55 * Direct Addressing - the slave address forms the control information (command
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H A Dpl35x-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
31 #define PL35X_NANDC_DRIVER_NAME "pl35x-nand-controller"
58 /* SMC ECC status register (RO) */
61 /* SMC ECC configuration register */
68 /* SMC ECC command 1 register */
74 /* SMC ECC command 2 register */
80 /* SMC ECC value registers (RO) */
126 * struct pl35x_nandc - NAND flash controller driver structure
134 * @ecc_buf: Temporary buffer to extract ECC bytes
162 if (section >= chip->ecc.steps) in pl35x_ecc_ooblayout16_ecc()
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H A Dtegra_nand.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
10 #include <linux/dma-mapping.h>
34 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
40 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
41 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
156 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
185 struct mtd_oob_region ecc; member
207 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
211 return -ERANGE; in tegra_nand_ooblayout_rs_ecc()
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H A Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
13 * The main visible difference is that NFCv1 only has Hamming ECC
14 * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
21 * or 4) and each chunk will have its own ECC "digest" of 6B at the
28 * +-------------------------------------------------------------+
29 * | Data 1 | ... | Data N | ECC 1 | ... | ECCN | Free OOB bytes |
30 * +-------------------------------------------------------------+
33 * ECC) sections and potentially an extra one to deal with
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/openbmc/u-boot/drivers/ddr/fsl/
H A Dlc_common_dimm_params.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2008-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP Semiconductor
39 if (mclk_ps < outpdimm->tckmin_x_ps) { in compute_cas_latency()
42 mclk_ps, outpdimm->tckmin_x_ps); in compute_cas_latency()
45 if (mclk_ps > outpdimm->tckmax_ps) { in compute_cas_latency()
47 mclk_ps, outpdimm->tckmax_ps); in compute_cas_latency()
51 caslat_actual = (outpdimm->taamin_ps + mclk_ps - 1) / mclk_ps; in compute_cas_latency()
55 retry--; in compute_cas_latency()
66 outpdimm->lowest_common_spd_caslat = caslat_actual; in compute_cas_latency()
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/openbmc/docs/designs/
H A Dvpd-collection.md5 Created: 2019-06-11
10 Field Replaceable Units (FRUs) today - one example is the BMC FRU. On OpenPower
12 format. As a part of its enterprise class servers, IBM will use the IPZ format
18 - Some of the VPD information such as FRU part number, serial number need to be
21 - Several use cases on the BMC require that the applications decide on a certain
26 - There are use cases for the BMC to send VPD data to the host
31 of certain parameters of the FRU (atypical - for FRUs that do not have an
39 Essentially, the IPZ VPD structure consists of key-value pairs called keywords.
52 - IPZ VPD has different records and keywords.
54 - IPZ VPD is required to implement and validate ECC as defined in the OpenPower
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/openbmc/linux/include/linux/mtd/
H A Drawnand.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
75 #define NAND_CMD_NONE -1
84 #define NAND_DATA_IFACE_CHECK_ONLY -1
87 * Constants for Hardware ECC
89 /* Reset Hardware ECC for read */
91 /* Reset Hardware ECC for write */
93 /* Enable Hardware ECC before syndrome is read back from flash */
98 * ecc.correct() returns -EBADMSG.
124 * Chip requires ready check on read (for auto-incremented sequential read).
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/openbmc/linux/drivers/mtd/nand/
H A Decc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic Error-Correcting Code (ECC) engine
10 * This file describes the abstraction of any NAND ECC engine. It has been
11 * designed to fit most cases, including parallel NANDs and SPI-NANDs.
13 * There are three main situations where instantiating this ECC engine makes
15 * - external: The ECC engine is outside the NAND pipeline, typically this
16 * is a software ECC engine, or an hardware engine that is
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
20 * controllers. In the pipeline case, the ECC bytes are
23 * - ondie: The ECC engine is inside the NAND pipeline, on the chip's side.
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/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_spd.c1 // SPDX-License-Identifier: GPL-2.0
159 u32 err_check_type; /* ECC , PARITY.. */
196 * Name: ddr3_get_dimm_num - Find number of dimms and their addresses
198 * Args: dimm_addr - array of dimm addresses
211 dimm_cur_addr--) { in ddr3_get_dimm_num()
214 /* Far-End DIMM must be connected */ in ddr3_get_dimm_num()
232 * Name: dimmSpdInit - Get the SPD parameters.
234 * Args: dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator.
235 * info - DIMM information structure.
260 /* No byte for error check in DDR3 SPD, use DDR2 convention */ in ddr3_spd_init()
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H A Dddr3_hw_training.c1 // SPDX-License-Identifier: GPL-2.0
64 puts("DDR3 Training Sequence - Ver 5.7."); in ddr3_print_version()
90 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 1\n"); in ddr3_hw_training()
104 /* Ignore ECC errors - if ECC is enabled */ in ddr3_hw_training()
174 * Xor Bypass - ECC support in AXP is currently available for 1:1 in ddr3_hw_training()
184 DEBUG_MAIN_S("DDR3 Training Sequence - Run with PBS.\n"); in ddr3_hw_training()
186 DEBUG_MAIN_S("DDR3 Training Sequence - Run without PBS.\n"); in ddr3_hw_training()
197 /* Set low - 100Mhz DDR Frequency by HW */ in ddr3_hw_training()
198 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Dfs High2Low)\n"); in ddr3_hw_training()
207 DEBUG_MAIN_S("DDR3 Training Sequence - Registered DIMM Low WL - SKIP\n"); in ddr3_hw_training()
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/openbmc/linux/arch/s390/include/uapi/asm/
H A Dpkey.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
31 /* Minimum size of a key blob */
45 /* the newer ioctls use a pkey_key_type enum for type information */
55 /* the newer ioctls use a pkey_key_size enum for key size information */
63 /* some of the newer ioctls use these flags */
118 __u16 cardnr; /* in: card to use or FFFF for any */
129 __u16 cardnr; /* in: card to use or FFFF for any */
141 __u16 cardnr; /* in: card to use or FFFF for any */
235 * (return -1 with errno ENODEV). You may use the PKEY_APQNS4KT ioctl to
239 * generating CCA cipher keys you can use one or more of the PKEY_KEYGEN_*
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/openbmc/linux/drivers/crypto/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
34 Use VIA PadLock for AES algorithm.
39 called padlock-aes.
48 Use VIA PadLock for SHA1/SHA256 algorithms.
53 called padlock-sha.
61 Say 'Y' here to use the AMD Geode LX processor on-board AES
65 will be called geode-aes.
101 kernel or userspace applications may use these functions.
119 AES cipher algorithms for use with protected key.
121 Select this option if you want to use the paes cipher
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/openbmc/linux/Documentation/admin-guide/
H A Dras.rst33 -------------
44 * Memory – add error correction logic (ECC) to detect and correct errors;
47 Self-Monitoring, Analysis and Reporting Technology (SMART).
55 ---------------
57 Most mechanisms used on modern systems use technologies like Hamming
68 * **Correctable Error (CE)** - the error detection mechanism detected and
72 * **Uncorrected Error (UE)** - the amount of errors happened above the error
73 correction threshold, and the system was unable to auto-correct.
75 * **Fatal Error** - when an UE error happens on a critical component of the
79 * **Non-fatal Error** - when an UE error happens on an unused component,
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/openbmc/linux/drivers/mtd/nand/raw/brcmnand/
H A Dbrcmnand.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2010-2015 Broadcom Corporation
17 #include <linux/dma-mapping.h>
89 #define FLASH_DMA_MODE_STOP_ON_ERROR BIT(1) /* stop in Uncorr ECC error */
237 /* List of NAND hosts (one for each chip-select) */
240 /* EDU info, per-transaction */
261 /* in-memory cache of the FLASH_CACHE, used only for some commands */
267 const u8 *cs_offsets; /* within each chip-select */
278 /* for low-power standby/resume only */
298 /* use for low-power standby/resume only */
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