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/openbmc/linux/drivers/input/touchscreen/
H A Dstmpe-ts.c1 // SPDX-License-Identifier: GPL-2.0-or-later
46 #define STMPE_TS_NAME "stmpe-ts"
50 * struct stmpe_touch - stmpe811 touch screen controller state
57 * (0 -> 1 sample, 1 -> 2 samples, 2 -> 4 samples, 3 -> 8 samples)
59 * (0 -> 10 us, 1 -> 50 us, 2 -> 100 us, 3 -> 500 us,
60 * 4-> 1 ms, 5 -> 5 ms, 6 -> 10 ms, 7 -> 50 ms)
63 * (0 -> 10 us, 1 -> 100 us, 2 -> 500 us, 3 -> 1 ms,
64 * 4 -> 5 ms, 5 -> 10 ms, 6 for 50 ms, 7 -> 100 ms)
70 * (0 -> 20 mA typical 35 mA max, 1 -> 50 mA typical 80 mA max)
101 u32 timeout = 40; in stmpe_work() local
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H A Dbcm_iproc_tsc.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #define IPROC_TS_NAME "iproc-ts"
88 regmap_read(priv->regmap, reg, &val); \
93 /* Each step is 1024 us. Valid 1-256 */
96 /* Each step is 512 us. Valid 0-255 */
100 * The settling duration (in ms) is the amount of time the tsc
102 * drivers in detection mode. Valid values: 0-11
103 * 0 = 0.008 ms
104 * 1 = 0.01 ms
105 * 2 = 0.02 ms
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/openbmc/linux/Documentation/devicetree/bindings/input/
H A Diqs626a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS626A is a 14-channel capacitive touch controller that features
14 additional Hall-effect and inductive sensing capabilities.
19 - $ref: touchscreen/touchscreen.yaml#
31 "#address-cells":
34 "#size-cells":
37 azoteq,suspend-mode:
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H A Dazoteq,iqs7222.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
21 - azoteq,iqs7222a
22 - azoteq,iqs7222b
23 - azoteq,iqs7222c
24 - azoteq,iqs7222d
29 irq-gpios:
32 Specifies the GPIO connected to the device's active-low RDY output.
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H A Diqs269a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS269A is an 8-channel capacitive touch controller that features
14 additional Hall-effect and inductive sensing capabilities.
28 "#address-cells":
31 "#size-cells":
34 azoteq,hall-enable:
37 Enables Hall-effect sensing on channels 6 and 7. In this case, keycodes
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/openbmc/linux/drivers/rtc/
H A Drtc-jz4740.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/clk-provider.h>
75 return readl(rtc->base + reg); in jz4740_rtc_reg_read()
82 return readl_poll_timeout(rtc->base + JZ_REG_RTC_CTRL, ctrl, in jz4740_rtc_wait_write_ready()
95 writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
97 return readl_poll_timeout(rtc->base + JZ_REG_RTC_WENR, ctrl, in jz4780_rtc_enable_write()
106 if (rtc->type >= ID_JZ4760) in jz4740_rtc_reg_write()
111 writel(val, rtc->base + reg); in jz4740_rtc_reg_write()
123 spin_lock_irqsave(&rtc->lock, flags); in jz4740_rtc_ctrl_set_bits()
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/openbmc/linux/drivers/pmdomain/samsung/
H A Dexynos-pm-domains.c1 // SPDX-License-Identifier: GPL-2.0
9 // conjunction with runtime-pm. Support for both device-tree and non-device-tree
40 u32 timeout, pwr; in exynos_pd_power() local
44 base = pd->base; in exynos_pd_power()
46 pwr = power_on ? pd->local_pwr_cfg : 0; in exynos_pd_power()
49 /* Wait max 1ms */ in exynos_pd_power()
50 timeout = 10; in exynos_pd_power()
52 while ((readl_relaxed(base + 0x4) & pd->local_pwr_cfg) != pwr) { in exynos_pd_power()
53 if (!timeout) { in exynos_pd_power()
55 pr_err("Power domain %s %s failed\n", domain->name, op); in exynos_pd_power()
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/openbmc/linux/drivers/watchdog/
H A Dts4800_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Watchdog driver for TS-4800 based boards
5 * Copyright (c) 2015 - Savoir-faire Linux
36 * TS-4800 supports the following timeout values:
39 * ---------------------
40 * 0 feed for 338ms
45 * Keep the regmap/timeout map ordered by timeout
48 const int timeout; member
55 #define MAX_TIMEOUT_INDEX (ARRAY_SIZE(ts4800_wdt_map) - 1)
59 regmap_write(wdt->regmap, wdt->feed_offset, val); in ts4800_write_feed()
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H A Dpika_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #define DRV_NAME "PIKA-WDT"
31 /* Hardware timeout in seconds */
34 /* Timer heartbeat (500ms) */
37 /* User land timeout */
71 /* -- FPGA: Reset Control Register (32bit R/W) (Offset: 0x14) -- in pikawdt_reset()
76 * Bit 8-11, WTCHDG_TIMEOUT_SEC: Sets the watchdog timeout value in in pikawdt_reset()
81 /* enable with max timeout - 15 seconds */ in pikawdt_reset()
118 return -EBUSY; in pikawdt_open()
157 return -EFAULT; in pikawdt_write()
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H A Dat91sam9_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr
11 * timeout need to be set from Linux, be sure that the bootstrap or the
41 readl_relaxed((wdt)->base + (field))
43 writel_relaxed((val), (wdt)->base + (field))
52 #define secs_to_ticks(s) ((s) ? (((s) << 8) - 1) : 0)
62 /* Hardware timeout in seconds */
65 /* Timer heartbeat (500ms) */
68 /* User land timeout */
123 if (time_before(jiffies, wdt->next_heartbeat) || in at91_ping()
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H A Dmt7621_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Ralink MT7621/MT7628 built-in hardware watchdog timer
61 rt_wdt_w32(drvdata->base, TIMER_REG_TMRSTAT, TMR1CTL_RESTART); in mt7621_wdt_ping()
70 w->timeout = t; in mt7621_wdt_set_timeout()
71 rt_wdt_w32(drvdata->base, TIMER_REG_TMR1LOAD, t * 1000); in mt7621_wdt_set_timeout()
82 /* set the prescaler to 1ms == 1000us */ in mt7621_wdt_start()
83 rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT); in mt7621_wdt_start()
85 mt7621_wdt_set_timeout(w, w->timeout); in mt7621_wdt_start()
87 t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL); in mt7621_wdt_start()
89 rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t); in mt7621_wdt_start()
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H A Dgpio_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for watchdog device controlled through GPIO-line
41 gpiod_set_value_cansleep(priv->gpiod, 1); in gpio_wdt_disable()
44 if (priv->hw_algo == HW_ALGO_TOGGLE) in gpio_wdt_disable()
45 gpiod_direction_input(priv->gpiod); in gpio_wdt_disable()
52 switch (priv->hw_algo) { in gpio_wdt_ping()
55 priv->state = !priv->state; in gpio_wdt_ping()
56 gpiod_set_value_cansleep(priv->gpiod, priv->state); in gpio_wdt_ping()
60 gpiod_set_value_cansleep(priv->gpiod, 1); in gpio_wdt_ping()
62 gpiod_set_value_cansleep(priv->gpiod, 0); in gpio_wdt_ping()
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H A Dqcom-wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
55 return wdt->base + wdt->layout[reg]; in wdt_addr()
76 unsigned int bark = wdd->timeout - wdd->pretimeout; in qcom_wdt_start()
80 writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME)); in qcom_wdt_start()
81 writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME)); in qcom_wdt_start()
103 unsigned int timeout) in qcom_wdt_set_timeout() argument
105 wdd->timeout = timeout; in qcom_wdt_set_timeout()
110 unsigned int timeout) in qcom_wdt_set_pretimeout() argument
112 wdd->pretimeout = timeout; in qcom_wdt_set_pretimeout()
120 u32 timeout; in qcom_wdt_restart() local
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/openbmc/linux/drivers/spi/
H A Dspi-sprd-adi.c4 * SPDX-License-Identifier: GPL-2.0
36 #define REG_ADI_CHN_ADDR(id) (0x44 + (id - 2) * 4)
69 /* Timeout (ms) for the trylock of hardware spinlocks */
125 /* Use default timeout 50 ms that converts to watchdog values */
159 if (reg >= sadi->data->slave_addr_size) { in sprd_adi_check_addr()
160 dev_err(sadi->dev, in sprd_adi_check_addr()
163 return -EINVAL; in sprd_adi_check_addr()
171 u32 timeout = ADI_FIFO_DRAIN_TIMEOUT; in sprd_adi_drain_fifo() local
175 sts = readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS); in sprd_adi_drain_fifo()
180 } while (--timeout); in sprd_adi_drain_fifo()
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/openbmc/linux/net/netfilter/ipvs/
H A Dip_vs_sync.c1 // SPDX-License-Identifier: GPL-2.0
6 * high-performance and highly available server based on a
13 * time-outs, and firewall marks.
15 * Ver. 0 can be turned on by sysctl -w net.ipv4.vs.sync_version=0
32 * Persistence support, fwmark and time-out.
61 #define IP_VS_SYNC_GROUP 0xe0000051 /* multicast addr - 224.0.0.81 */
100 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
102 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
104 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
106 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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/openbmc/linux/drivers/nfc/
H A Dtrf7970a.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
39 * when EN2 is left low. The 'en2-rf-quirk' device tree property
46 * interrupts, however. That is, an interrupt and a timeout could occur
48 * executes. When the timeout handler executes first and blocks the
51 * When the interrupt handler executes first and blocks the timeout handler,
53 * work item (i.e., timeout) and will return zero. That return code is
54 * used by the timer handler to indicate that it should ignore the timeout
62 * has sent the command to the tag, it simply returns -ECANCELED. If the
65 * sending the data upstream, it frees the rx_skb and sends -ECANCELED
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/openbmc/linux/arch/arm/mach-exynos/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 // Cloned from linux/arch/arm/mach-vexpress/platsmp.c
17 #include <linux/soc/samsung/exynos-regs-pmu.h>
29 /* XXX exynos_pen_release is cargo culted code - DO NOT COPY XXX */
30 volatile int exynos_pen_release = -1;
70 * having been woken up - this shouldn't happen in platform_do_lowpower()
72 * Just note it happening - when we're woken, we can report in platform_do_lowpower()
81 * exynos_cpu_power_down() - power down the specified cpu
109 * exynos_cpu_power_up() - power up the specified cpu
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/openbmc/linux/drivers/mmc/host/
H A Dsdhci-of-esdhc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
22 #include <linux/dma-mapping.h>
26 #include "sdhci-pltfm.h"
27 #include "sdhci-esdhc.h"
71 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
72 { .compatible = "fsl,ls1043a-esdhc", .data = &ls1043a_esdhc_clk},
73 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
74 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
75 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk},
76 { .compatible = "fsl,mpc8379-esdhc" },
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/openbmc/linux/drivers/nvmem/
H A Dsc27xx-efuse.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/nvmem-provider.h>
46 /* Timeout (ms) for the trylock of hardware spinlocks */
49 /* Timeout (us) of polling the status */
79 * On Spreadtrum platform, we have multi-subsystems will access the unique
87 mutex_lock(&efuse->mutex); in sc27xx_efuse_lock()
89 ret = hwspin_lock_timeout_raw(efuse->hwlock, in sc27xx_efuse_lock()
92 dev_err(efuse->dev, "timeout to get the hwspinlock\n"); in sc27xx_efuse_lock()
93 mutex_unlock(&efuse->mutex); in sc27xx_efuse_lock()
102 hwspin_unlock_raw(efuse->hwlock); in sc27xx_efuse_unlock()
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/openbmc/linux/drivers/usb/musb/
H A Dux500.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010 ST-Ericsson AB
16 #include <linux/usb/musb-ux500.h>
32 #define glue_to_musb(g) platform_get_drvdata(g->musb)
37 unsigned long timeout = jiffies + msecs_to_jiffies(1000); in ux500_musb_set_vbus() local
43 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); in ux500_musb_set_vbus()
46 if (musb->xceiv->otg->state == OTG_STATE_A_IDLE) { in ux500_musb_set_vbus()
49 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); in ux500_musb_set_vbus()
54 while (musb_readb(musb->mregs, MUSB_DEVCTL) & 0x80) { in ux500_musb_set_vbus()
56 if (time_after(jiffies, timeout)) { in ux500_musb_set_vbus()
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/openbmc/linux/drivers/i2c/busses/
H A Di2c-ocores.c1 // SPDX-License-Identifier: GPL-2.0
3 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
22 #include <linux/platform_data/i2c-ocores.h>
87 #define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */
91 iowrite8(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_8()
96 iowrite16(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_16()
101 iowrite32(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_32()
106 iowrite16be(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_16be()
111 iowrite32be(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_32be()
116 return ioread8(i2c->base + (reg << i2c->reg_shift)); in oc_getreg_8()
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/openbmc/linux/drivers/cpufreq/
H A Dbrcmstb-avs-cpufreq.c32 * DVFS. The AVS firmware is running on its own co-processor. The
93 /* PMAP and P-STATE commands */
107 * unused:31-24, mdiv_p0:23-16, unused:15-14, pdiv:13-10 , ndiv_int:9-0
117 * mdiv_p4:31-24, mdiv_p3:23-16, mdiv_p2:15:8, mdiv_p1:7:0
128 /* Different P-STATES AVS supports (for GET_PSTATE/SET_PSTATE) */
148 /* Non-AVS modes are not supported */
150 /* Cannot set P-State until P-Map supplied */
152 /* Cannot change P-Map after initial P-Map set */
159 #define AVS_TIMEOUT 300 /* in ms; expected completion is < 10ms */
162 #define BRCM_AVS_CPUFREQ_PREFIX "brcmstb-avs"
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/openbmc/linux/sound/soc/codecs/
H A Dwcd-mbhc-v2.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
14 #include "wcd-mbhc-v2.h"
72 /* Holds type of Headset - Mono/Stereo */
74 /* Holds mbhc detection method - ADC/Legacy */
81 if (!mbhc->fields[field].reg) in wcd_mbhc_write_field()
84 return snd_soc_component_write_field(mbhc->component, in wcd_mbhc_write_field()
85 mbhc->fields[field].reg, in wcd_mbhc_write_field()
86 mbhc->fields[field].mask, val); in wcd_mbhc_write_field()
91 if (!mbhc->fields[field].reg) in wcd_mbhc_read_field()
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/openbmc/linux/drivers/media/rc/
H A Dst_rc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <media/rc-core.h>
49 * IRQ set: Enable full FIFO 1 -> bit 3;
50 * Enable overrun IRQ 1 -> bit 2;
51 * Enable last symbol IRQ 1 -> bit 1:
52 * Enable RX interrupt 1 -> bit 0;
56 /* maximum symbol period (microsecs),timeout to detect end of symbol train */
62 #define IR_ST_NAME "st-rc"
66 struct ir_raw_event ev = { .timeout = true, .duration = rdev->timeout }; in st_rc_send_lirc_timeout()
75 * |-IRB_RX_ON-| |-IRB_RX_ON-|
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/openbmc/linux/drivers/tty/serial/
H A Dar933x_uart.c1 // SPDX-License-Identifier: GPL-2.0
3 * Atheros AR933X SoC built-in UART driver
31 #include <asm/mach-ath79/ar933x_uart.h>
35 #define DRIVER_NAME "ar933x-uart"
60 return readl(up->port.membase + offset); in ar933x_uart_read()
66 writel(value, up->port.membase + offset); in ar933x_uart_write()
98 up->ier |= AR933X_UART_INT_TX_EMPTY; in ar933x_uart_start_tx_interrupt()
99 ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); in ar933x_uart_start_tx_interrupt()
104 up->ier &= ~AR933X_UART_INT_TX_EMPTY; in ar933x_uart_stop_tx_interrupt()
105 ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); in ar933x_uart_stop_tx_interrupt()
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