/openbmc/linux/Documentation/devicetree/bindings/net/ |
H A D | ti,dp83867.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/net/ti,dp83867.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: TI DP83867 ethernet PHY 11 - $ref: ethernet-controller.yaml# 14 - Andrew Davis <afd@ti.com> 17 The DP83867 device is a robust, low power, fully featured Physical Layer 18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX 19 and 1000BASE-T Ethernet protocols. [all …]
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H A D | ti,k3-am654-cpsw-nuss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller) 10 - Grygorii Strashko <grygorii.strashko@ti.com> 11 - Sekhar Nori <nsekhar@ti.com> 14 The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports 16 The TI AM642x SoC Gigabit Ethernet MAC (CPSW3G NUSS) has three ports 22 Complex (UDMA-P) controller. [all …]
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/openbmc/u-boot/drivers/net/phy/ |
H A D | ti.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * TI PHY drivers 12 #include <dt-bindings/net/ti-dp83867.h> 15 /* TI DP83867 */ 86 /* User setting - can be taken from DTS */ 120 * phy_read_mmd_indirect - reads data from the MMD registers 137 int value = -1; in phy_read_mmd_indirect() 154 * phy_write_mmd_indirect - writes data to the MMD registers 187 struct dp83867_private *dp83867 = in dp83867_config_port_mirroring() local 188 (struct dp83867_private *)phydev->priv; in dp83867_config_port_mirroring() [all …]
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/openbmc/linux/drivers/net/phy/ |
H A D | dp83867.c | 1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83867 PHY 17 #include <linux/nvmem-consumer.h> 19 #include <dt-bindings/net/ti-dp83867.h> 194 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol() 201 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol() 206 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol() 207 mac = (const u8 *)ndev->dev_addr; in dp83867_set_wol() 210 return -EINVAL; in dp83867_set_wol() 224 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83867_set_wol() [all …]
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/openbmc/u-boot/doc/device-tree-bindings/net/ |
H A D | ti,dp83867.txt | 1 * Texas Instruments - dp83867 Giga bit ethernet phy 4 - reg - The ID number for the phy, usually a small integer 5 - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h 7 - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h 9 - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h 11 - enet-phy-lane-swap - Indicates that PHY will swap the TX/RX lanes to 13 - enet-phy-no-lane-swap - Indicates that PHY will disable swap of the 15 - ti,clk-output-sel - Clock output select - see dt-bindings/net/ti-dp83867.h 23 ethernet-phy@0 { 25 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | dra72-evm-revc.dts | 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 8 #include "dra72-evm-common.dtsi" 9 #include "dra72x-mmc-iodelay.dtsi" 10 #include <dt-bindings/net/ti-dp83867.h> 13 model = "TI DRA722 Rev C EVM"; 20 evm_1v8_sw: fixedregulator-evm_1v8 { 21 compatible = "regulator-fixed"; 22 regulator-name = "evm_1v8"; 23 regulator-min-microvolt = <1800000>; 24 regulator-max-microvolt = <1800000>; [all …]
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H A D | dra71-evm.dts | 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 9 #include "dra72-evm-common.dtsi" 10 #include "dra72x-mmc-iodelay.dtsi" 11 #include <dt-bindings/net/ti-dp83867.h> 14 compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7"; 15 model = "TI DRA718 EVM"; 22 vpo_sd_1v8_3v3: gpio-regulator-TPS74801 { 23 compatible = "regulator-gpio"; 25 regulator-name = "vddshv8"; 26 regulator-min-microvolt = <1800000>; [all …]
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H A D | dra76-evm.dts | 2 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ 8 /dts-v1/; 11 #include "dra7-evm-common.dtsi" 12 #include "dra76x-mmc-iodelay.dtsi" 13 #include <dt-bindings/net/ti-dp83867.h> 16 model = "TI DRA762 EVM"; 17 compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7"; 24 vsys_12v0: fixedregulator-vsys12v0 { 26 compatible = "regulator-fixed"; 27 regulator-name = "vsys_12v0"; [all …]
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/openbmc/linux/arch/arm/boot/dts/ti/omap/ |
H A D | dra72-evm-revc.dts | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ 5 #include "dra72-evm-common.dtsi" 6 #include "dra72x-mmc-iodelay.dtsi" 7 #include <dt-bindings/net/ti-dp83867.h> 10 model = "TI DRA722 Rev C EVM"; 17 reserved-memory { 18 #address-cells = <2>; 19 #size-cells = <2>; 23 compatible = "shared-dma-pool"; [all …]
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H A D | dra71-evm.dts | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ 7 #include "dra7-mmc-iodelay.dtsi" 8 #include "dra72x-mmc-iodelay.dtsi" 9 #include <dt-bindings/net/ti-dp83867.h> 12 compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7"; 13 model = "TI DRA718 EVM"; 20 reserved-memory { 21 #address-cells = <2>; 22 #size-cells = <2>; [all …]
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H A D | dra76-evm.dts | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ 5 /dts-v1/; 8 #include "dra7-evm-common.dtsi" 9 #include "dra76x-mmc-iodelay.dtsi" 10 #include <dt-bindings/net/ti-dp83867.h> 13 model = "TI DRA762 EVM"; 14 compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7"; 28 reserved-memory { 29 #address-cells = <2>; [all …]
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/openbmc/linux/arch/arm64/boot/dts/xilinx/ |
H A D | zynqmp-zcu102-revB.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * (C) Copyright 2016 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 11 #include "zynqmp-zcu102-revA.dts" 15 compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 19 phy-handle = <&phyc>; 21 phyc: ethernet-phy@c { 22 #phy-cells = <0x1>; 23 compatible = "ethernet-phy-id2000.a231"; 25 ti,rx-internal-delay = <0x8>; [all …]
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H A D | zynqmp-sck-kv-g-revB.dtso | 1 // SPDX-License-Identifier: GPL-2.0 5 * (C) Copyright 2020 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/net/ti-dp83867.h> 13 #include <dt-bindings/phy/phy.h> 14 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 16 /dts-v1/; 20 si5332_0: si5332-0 { /* u17 */ 21 compatible = "fixed-clock"; [all …]
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H A D | zynqmp-sck-kv-g-revA.dtso | 1 // SPDX-License-Identifier: GPL-2.0 5 * (C) Copyright 2020 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 9 * "A" - A01 board un-modified (NXP) 10 * "Y" - A01 board modified with legacy interposer (Nexperia) 11 * "Z" - A01 board modified with Diode interposer 16 #include <dt-bindings/gpio/gpio.h> 17 #include <dt-bindings/net/ti-dp83867.h> 18 #include <dt-bindings/phy/phy.h> 19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> [all …]
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/openbmc/linux/arch/arm64/boot/dts/freescale/ |
H A D | mba8mx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 3 * Copyright 2020-2021 TQ-Systems GmbH 6 #include <dt-bindings/net/ti-dp83867.h> 8 /* TQ-Systems GmbH MBa8Mx baseboard */ 12 compatible = "pwm-beeper"; 14 beeper-hz = <4000>; 15 amp-supply = <®_vcc_3v3>; 19 stdout-path = &uart3; 22 gpio-keys { 23 compatible = "gpio-keys"; [all …]
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H A D | imx93-tqma9352-mba93xxla.dts | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 3 * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, 4 * D-82229 Seefeld, Germany. 8 /dts-v1/; 10 #include <dt-bindings/input/input.h> 11 #include <dt-bindings/leds/common.h> 12 #include <dt-bindings/net/ti-dp83867.h> 13 #include <dt-bindings/pwm/pwm.h> 14 #include <dt-bindings/usb/pd.h> 15 #include "imx93-tqma9352.dtsi" [all …]
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H A D | imx8mp-tqma8mpql-mba8mpxl.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 3 * Copyright 2021-2022 TQ-Systems GmbH 4 * Author: Alexander Stein <alexander.stein@tq-group.com> 7 /dts-v1/; 9 #include <dt-bindings/leds/common.h> 10 #include <dt-bindings/net/ti-dp83867.h> 11 #include <dt-bindings/phy/phy-imx8-pcie.h> 12 #include <dt-bindings/pwm/pwm.h> 13 #include "imx8mp-tqma8mpql.dtsi" 16 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL"; [all …]
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H A D | imx8mp-phycore-som.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 7 #include <dt-bindings/net/ti-dp83867.h> 11 model = "PHYTEC phyCORE-i.MX8MP"; 12 compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp"; 26 cpu-supply = <&buck2>; 30 cpu-supply = <&buck2>; 34 cpu-supply = <&buck2>; 38 cpu-supply = <&buck2>; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_fec>; [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/ls/ |
H A D | ls1021a-tqmls1021a-mbls1021a.dts | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR X11) 3 * Copyright 2013-2014 Freescale Semiconductor, Inc. 4 * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, 5 * D-82229 Seefeld, Germany. 9 /dts-v1/; 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/input/linux-event-codes.h> 13 #include <dt-bindings/leds/common.h> 14 #include <dt-bindings/leds/leds-pca9532.h> 15 #include <dt-bindings/net/ti-dp83867.h> [all …]
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/openbmc/linux/arch/arm64/boot/dts/ti/ |
H A D | k3-j721s2-evm-gesi-exp-board.dtso | 1 // SPDX-License-Identifier: GPL-2.0 5 * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM 7 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 10 /dts-v1/; 13 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/net/ti-dp83867.h> 16 #include "k3-pinctrl.h" 20 ethernet1 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1"; 25 main_cpsw_mdio_default_pins: main-cpsw-mdio-default-pins { 26 pinctrl-single,pins = < [all …]
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H A D | k3-j721e-evm-gesi-exp-board.dtso | 1 // SPDX-License-Identifier: GPL-2.0 6 * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM 8 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 11 /dts-v1/; 14 #include <dt-bindings/gpio/gpio.h> 15 #include <dt-bindings/net/ti-dp83867.h> 17 #include "k3-pinctrl.h" 21 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; 22 ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; 23 ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3"; [all …]
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H A D | k3-am64-phycore-som.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com 10 * https://www.phytec.com/product/phycore-am64x 13 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/leds/common.h> 15 #include <dt-bindings/net/ti-dp83867.h> 18 model = "PHYTEC phyCORE-AM64x"; 19 compatible = "phytec,am64-phycore-som", "ti,am642"; 32 reserved-memory { 33 #address-cells = <2>; [all …]
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/openbmc/u-boot/include/dt-bindings/net/ |
H A D | ti-dp83867.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 3 * TI DP83867 PHY drivers 34 /* IO_MUX_CFG - Clock output selection */
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/openbmc/linux/include/dt-bindings/net/ |
H A D | ti-dp83867.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * Device Tree constants for the Texas Instruments DP83867 PHY 5 * Author: Dan Murphy <dmurphy@ti.com> 37 /* IO_MUX_CFG - Clock output selection */
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/openbmc/linux/arch/arm/boot/dts/ti/keystone/ |
H A D | keystone-k2g-ice.dts | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ 7 /dts-v1/; 9 #include "keystone-k2g.dtsi" 10 #include <dt-bindings/net/ti-dp83867.h> 13 compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone"; 21 reserved-memory { 22 #address-cells = <2>; 23 #size-cells = <2>; 26 dsp_common_memory: dsp-common-memory@81f800000 { [all …]
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