1ef797b53SMichal Simek// SPDX-License-Identifier: GPL-2.0+ 2ef797b53SMichal Simek/* 3ef797b53SMichal Simek * dts file for Xilinx ZynqMP ZCU102 RevB 4ef797b53SMichal Simek * 5*c720a1f5SMichal Simek * (C) Copyright 2016 - 2022, Xilinx, Inc. 6*c720a1f5SMichal Simek * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 7ef797b53SMichal Simek * 84e4ddd3dSMichal Simek * Michal Simek <michal.simek@amd.com> 9ef797b53SMichal Simek */ 10ef797b53SMichal Simek 11ef797b53SMichal Simek#include "zynqmp-zcu102-revA.dts" 12ef797b53SMichal Simek 13ef797b53SMichal Simek/ { 14ef797b53SMichal Simek model = "ZynqMP ZCU102 RevB"; 15ef797b53SMichal Simek compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 16ef797b53SMichal Simek}; 17ef797b53SMichal Simek 18ef797b53SMichal Simek&gem3 { 19ef797b53SMichal Simek phy-handle = <&phyc>; 20*c720a1f5SMichal Simek mdio: mdio { 2113d21ebaSMichal Simek phyc: ethernet-phy@c { 22*c720a1f5SMichal Simek #phy-cells = <0x1>; 23*c720a1f5SMichal Simek compatible = "ethernet-phy-id2000.a231"; 24ef797b53SMichal Simek reg = <0xc>; 25ef797b53SMichal Simek ti,rx-internal-delay = <0x8>; 26ef797b53SMichal Simek ti,tx-internal-delay = <0xa>; 27ef797b53SMichal Simek ti,fifo-depth = <0x1>; 2878c484a5SHarini Katakam ti,dp83867-rxctrl-strap-quirk; 29*c720a1f5SMichal Simek reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; 30ef797b53SMichal Simek }; 31ef797b53SMichal Simek /* Cleanup from RevA */ 3213d21ebaSMichal Simek /delete-node/ ethernet-phy@21; 33ef797b53SMichal Simek }; 34*c720a1f5SMichal Simek}; 35ef797b53SMichal Simek 36ef797b53SMichal Simek/* Fix collision with u61 */ 37ef797b53SMichal Simek&i2c0 { 38ef797b53SMichal Simek i2c-mux@75 { 39ef797b53SMichal Simek i2c@2 { 40ef797b53SMichal Simek max15303@1b { /* u8 */ 41ef797b53SMichal Simek compatible = "maxim,max15303"; 42ef797b53SMichal Simek reg = <0x1b>; 43ef797b53SMichal Simek }; 44ef797b53SMichal Simek /delete-node/ max15303@20; 45ef797b53SMichal Simek }; 46ef797b53SMichal Simek }; 47ef797b53SMichal Simek}; 48