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/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Delpida_ecb240abacn.dtsi31 tRAS-min = <42000>;
42 tRAS-max-ns = <70000>;
53 tRAS-min = <42000>;
64 tRAS-max-ns = <70000>;
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr2-timings.yaml48 tRAS-max-ns:
52 tRAS-min:
123 tRAS-max-ns = <70000>;
124 tRAS-min = <42000>;
H A Djedec,lpddr2.yaml170 tRAS-min = <42000>;
181 tRAS-max-ns = <70000>;
191 tRAS-min = <42000>;
202 tRAS-max-ns = <70000>;
H A Djedec,lpddr3.yaml81 tRAS-min-tck:
204 tRAS-min-tck = <5>;
229 tRAS = <23000>;
H A Djedec,lpddr3-timings.yaml59 tRAS:
143 tRAS = <23000>;
/openbmc/linux/drivers/memory/
H A Dof_memory.c73 ret |= of_property_read_u32(np, "tRAS-min", &tim->tRAS_min); in of_do_get_timings()
84 ret |= of_property_read_u32(np, "tRAS-max-ns", &tim->tRAS_max_ns); in of_do_get_timings()
181 ret |= of_property_read_u32(np, "tRAS-min-tck", &min->tRAS); in of_lpddr3_get_min_tck()
227 ret |= of_property_read_u32(np, "tRAS", &tim->tRAS); in of_lpddr3_do_get_timings()
H A Djedec_ddr.h234 u32 tRAS; member
263 u32 tRAS; member
/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg55 # bit3-0: 0xf, 16 cycle tRAS (tRAS[3-0])
60 # bit20: 0, 16 cycle tRAS (tRAS[4])
H A Dkwbimage-lsxhl.cfg55 # bit3-0: 0x1, 18 cycle tRAS (tRAS[3-0])
60 # bit20: 1, 18 cycle tRAS (tRAS[4])
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg52 # bit3-0: 1, 18 cycle tRAS (tRAS[3-0])
57 # bit20: 1, 18 cycle tRAS (tRAS[4])
/openbmc/u-boot/board/work-microwave/work_92105/
H A Dwork_92105_spl.c24 .tras = 20833333,
44 .tras = 22222222,
/openbmc/u-boot/arch/arm/mach-sunxi/dram_timings/
H A Dddr2_v3s.c20 u8 tras = ns_to_t(45); in mctl_set_timing_params() local
55 DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), in mctl_set_timing_params()
H A Dlpddr3_stock.c20 u8 tras = ns_to_t(42); in mctl_set_timing_params() local
54 DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), in mctl_set_timing_params()
H A Dddr3_1333.c20 u8 tras = ns_to_t(38); in mctl_set_timing_params() local
58 DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), in mctl_set_timing_params()
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dlpddr2.h40 #define MMDC_MDCFG1_VALUE 0x00180E63 /* tRCD=n/a,tRPpb=n/a,tRC=n/a ,tRAS=25 (=47ns),tRPA=n/a,tWR…
42 #define MMDC_MDCFG3LP_VALUE 0x001F099B /* RC_LP=tRAS+tRPab=32 (>60ns), tRCD_LP=10 (18ns) , tRPpb…
/openbmc/u-boot/include/
H A Dspd.h45 unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ member
H A Dddr_spd.h45 unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ member
107 unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ member
203 unsigned char tras_trc_ext; /* 21 Upper Nibbles for tRAS and tRC */
320 uint8_t tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_rk3036.h53 u32 tras; member
250 u32 tras; member
/openbmc/u-boot/board/Seagate/dockstar/
H A Dkwbimage.cfg45 # bit3-0: TRAS lsbs
50 # bit20: TRAS msb
/openbmc/u-boot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg46 # bit3-0: TRAS lsbs
51 # bit20: TRAS msb
/openbmc/u-boot/board/iomega/iconnect/
H A Dkwbimage.cfg42 # bit3-0: TRAS lsbs
47 # bit20: TRAS msb
/openbmc/u-boot/board/Synology/ds109/
H A Dkwbimage.cfg46 # bit3-0: TRAS lsbs
51 # bit20: TRAS msb
/openbmc/u-boot/board/Seagate/goflexhome/
H A Dkwbimage.cfg48 # bit3-0: TRAS lsbs
53 # bit20: TRAS msb
/openbmc/u-boot/board/Marvell/dreamplug/
H A Dkwbimage.cfg43 # bit3-0: TRAS lsbs
48 # bit20: TRAS msb
/openbmc/u-boot/board/Marvell/sheevaplug/
H A Dkwbimage.cfg42 # bit3-0: TRAS lsbs
47 # bit20: TRAS msb

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