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/openbmc/u-boot/board/freescale/p1010rdb/
H A DREADME.P1010RDB-PB66 SW3[1:8]= 10010000
73 SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot
74 SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot
75 SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot
76 SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot
153 set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
157 set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
162 Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board
168 set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board
175 set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board
/openbmc/u-boot/board/freescale/ls1088a/
H A DREADME18 SW3 1111 0010
25 SW3 1111 0010
32 SW3 1111 0010
91 SW3 to SW12 are identical for all boot source
93 SW3 0010 0100
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dltc3676.txt8 - regulators: Contains eight regulator child nodes sw1, sw2, sw3, sw4,
13 nodes for sw1, sw2, sw3, sw4, ldo1, ldo2 and ldo4 additionally need to specify
20 Regulators sw1, sw2, sw3, sw4 can regulate the feedback reference from:
54 sw3_reg: sw3 {
H A Dltc3589.txt8 - regulators: Contains eight regulator child nodes sw1, sw2, sw3, bb-out,
13 nodes for sw1, sw2, sw3, bb-out, ldo1, and ldo2 additionally need to specify
20 Regulators sw1, sw2, sw3, and ldo2 can regulate the feedback reference from
54 sw3_reg: sw3 {
H A Dpv88060.txt11 BUCK1, LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, SW1, SW2, SW3, SW4,
97 SW3 {
98 regulator-name = "sw3";
H A Dpfuze100.yaml19 sw1a,sw1b,sw2,sw3,swbst,vsnvs,vrefddr,vldo1,vldo2,vccsd,v33,vldo3,vldo4
21 sw1,sw2,sw3,vsnvs,vldo1,vldo2,vccsd,v33,vldo3,vldo4
/openbmc/u-boot/doc/
H A DREADME.mpc85xxcds134 SW3=11101111
142 frequency can be changed by setting SW3:
146 SW3=XX00XXXX == CORE:CCB 2:1
159 SW3=00001000
173 SW3=11001000 (8X) (2:1)
176 SW3=X000XXXX == CORE:CCB 4:1
H A DREADME.b4860qds124 SW3 OFF OFF OFF ON OFF OFF ON OFF
136 SW3 [1:4] = 0001
140 SW3 [1:4] = 1000.
149 SW3 OFF OFF OFF ON OFF OFF ON OFF
161 SW3 [1:4] = 0001
165 SW3 [1:4] = 1000.
/openbmc/u-boot/board/freescale/t102xrdb/
H A DREADME194 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
196 set SW1[1:8] = '00010111', SW2[1] = '1', SW3[4] = '0' for NOR boot
202 via DIP-switch: set SW3[5:7] = '100'
205 via DIP-switch: set SW3[5:7] = '100'
210 via DIP-Switch: set SW3[5:7] = '000'
213 via DIP-switch: set SW3[5:7] = '000'
223 set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
250 SW3[3] = '1' for SD card(or 'switch sd' by software)
251 SW3[3] = '0' for eMMC (or 'switch emmc' by software)
/openbmc/u-boot/board/freescale/t104xrdb/
H A DREADME288 SW3: 11100001
293 SW3: 11110001
298 SW3: 11100001
303 SW3: 11100001
310 SW3: 11100001
315 SW3: 11110001
320 SW3: 11100001
325 SW3: 11100001
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dmc13xxx.txt59 sw3 : regulator SW3 (register 29, bit 20)
88 sw3 : regulator SW3 (register 26, bit 0)
/openbmc/u-boot/board/sbc8548/
H A DREADME216 SW3.1 CFG_HOST_AGT0 1* 0
217 SW3.2 CFG_HOST_AGT1 1* 0
218 SW3.3 CFG_HOST_AGT2 1* 0
219 SW3.4 CFG_IO_PORTS0 1* 0
220 SW3.5 CFG_IO_PORTS0 1 0*
221 SW3.6 CFG_IO_PORTS0 1 0*
/openbmc/u-boot/board/freescale/t208xrdb/
H A DREADME143 SW3[1:8] = '11100001'
154 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
159 via DIP-switch: set SW3[5:7] = '100'
163 via DIP-Switch: set SW3[5:7] = '000'
173 set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
/openbmc/u-boot/board/freescale/corenet_ds/
H A Dcorenet_ds.c74 /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */ in checkboard()
75 /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */ in checkboard()
76 /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */ in checkboard()
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx53-qsrb.dts58 sw3_reg: sw3 {
59 regulator-name = "SW3";
/openbmc/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx28-eukrea-mbmx28lc.dtsi27 switch-sw3 {
28 label = "SW3";
182 gpio_button_sw3_pins_mbmx28lc: gpio-button-sw3-mbmx28lc@0 {
/openbmc/u-boot/board/freescale/mpc832xemds/
H A DREADME17 SW3 is switch 18 as silk-screened onto the board.
28 SW3[1-8]= 0000_1000 (core PLL setting, core enable)
/openbmc/linux/drivers/hid/
H A Dhid-ite.c31 /* For Acer Aspire Switch 10E (SW3-016) keyboard-dock */ in ite_report_fixup()
33 hid_info(hdev, "Fixing up Acer Aspire Switch 10E (SW3-016) ITE keyboard report descriptor\n"); in ite_report_fixup()
/openbmc/linux/Documentation/hid/
H A Dhid-alps.rst114 1 0 0 SW6 SW5 SW4 SW3 SW2 SW1
164 Byte1 1 1 1 0 1 SW3 SW2 SW1
173 SW1-SW3:
/openbmc/linux/drivers/media/dvb-frontends/
H A Ddib0090.h87 extern int dib0090_set_switch(struct dvb_frontend *fe, u8 sw1, u8 sw2, u8 sw3);
157 u8 sw1, u8 sw2, u8 sw3) in dib0090_set_switch() argument
/openbmc/u-boot/board/liebherr/display5/
H A Ddisplay5.c52 #define SW3 IMX_GPIO_NR(2, 7) macro
63 SW0, SW1, SW2, SW3
67 "sw0", "sw1", "sw2", "sw3"
/openbmc/u-boot/board/phytec/pfla02/
H A DREADME21 The dip switch "SW3" on the board let choose the boot device.
/openbmc/linux/drivers/regulator/
H A Dltc3676.c172 /* SW1, SW2, SW3, SW4 linear 0.8V-3.3V with scalar via R1/R2 feeback res */
227 LTC3676_LINEAR_REG(SW3, sw3, BUCK3, DVB3A),
H A Dltc3589.c130 /* SW1, SW2, SW3, LDO2 */
258 LTC3589_LINEAR_REG(SW3, sw3, B3DTV1),
/openbmc/u-boot/board/freescale/mpc8641hpcn/
H A DREADME43 SW3(1-7) = 0011000 CONFIG_SYS_VID = 0011000 :: VCORE = 1.2V
45 SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V

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