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/openbmc/linux/Documentation/devicetree/bindings/arm/msm/
H A Dqcom,saw2.txt5 power-controller that transitions a piece of hardware (like a processor or
10 Multiple revisions of the SAW hardware are supported using these Device Nodes.
12 same revision of the SAW in different SoCs may have different configuration
14 version of the SAW hardware in that SoC and the distinction between cpu (big
15 or Little) or cache, may be needed to uniquely identify the SAW register
21 - compatible:
27 "qcom,apq8064-saw2-v1.1-cpu"
28 "qcom,msm8226-saw2-v2.1-cpu"
29 "qcom,msm8974-saw2-v2.1-cpu"
30 "qcom,apq8084-saw2-v2.1-cpu"
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,spm.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
20 - enum:
21 - qcom,sdm660-gold-saw2-v4.1-l2
22 - qcom,sdm660-silver-saw2-v4.1-l2
23 - qcom,msm8998-gold-saw2-v4.1-l2
24 - qcom,msm8998-silver-saw2-v4.1-l2
[all …]
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dqcom,spmi-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/qcom,spmi-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Robert Marko <robimarko@gmail.com>
15 - qcom,pm6125-regulators
16 - qcom,pm660-regulators
17 - qcom,pm660l-regulators
18 - qcom,pm8004-regulators
19 - qcom,pm8005-regulators
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/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-ipq4019.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
18 interrupt-parent = <&intc>;
20 reserved-memory {
21 #address-cells = <0x1>;
[all …]
H A Dqcom-apq8084.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
6 #include <dt-bindings/gpio/gpio.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
13 interrupt-parent = <&intc>;
15 reserved-memory {
16 #address-cells = <1>;
[all …]
H A Dqcom-msm8960.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
8 #include <dt-bindings/mfd/qcom-rpm.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
H A Dqcom-msm8974.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
10 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
[all …]
H A Dqcom-apq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
[all …]
H A Dqcom-apq8060-dragonboard.dts1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/leds/common.h>
5 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
6 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
7 #include "qcom-msm8660.dtsi"
11 compatible = "qcom,apq8060-dragonboard", "qcom,msm8660";
18 stdout-path = "serial0:115200n8";
22 vph: regulator-fixed {
[all …]
H A Dqcom-ipq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
11 #include <dt-bindings/soc/qcom,gsbi.h>
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8996-xiaomi-common.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
15 compatible = "gpio-gate-clock";
17 #clock-cells = <0>;
18 enable-gpios = <&pm8994_gpios 15 GPIO_ACTIVE_HIGH>;
20 pinctrl-names = "default";
21 pinctrl-0 = <&divclk1_default>;
[all …]
H A Dmsm8996-oneplus-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
12 #include <dt-bindings/sound/qcom,q6afe.h>
13 #include <dt-bindings/sound/qcom,q6asm.h>
14 #include <dt-bindings/sound/qcom,wcd9335.h>
23 compatible = "simple-battery";
25 constant-charge-current-max-microamp = <3000000>;
26 voltage-min-design-microvolt = <3400000>;
30 stdout-path = "serial1:115200n8";
[all …]
H A Dmsm8996-sony-xperia-tone.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
16 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
18 /delete-node/ &adsp_mem;
19 /delete-node/ &slpi_mem;
20 /delete-node/ &venus_mem;
21 /delete-node/ &gpu_mem;
[all …]
H A Dmsm8939.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8939.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8939.h>
13 #include <dt-bindings/thermal/thermal.h>
[all …]
H A Dapq8096-db820c.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
6 /dts-v1/;
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
15 #include <dt-bindings/sound/qcom,q6afe.h>
16 #include <dt-bindings/sound/qcom,q6asm.h>
17 #include <dt-bindings/sound/qcom,wcd9335.h>
[all …]
H A Dmsm8916.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8916.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
13 #include <dt-bindings/thermal/thermal.h>
[all …]
/openbmc/linux/drivers/tty/serial/jsm/
H A Djsm.h1 /* SPDX-License-Identifier: GPL-2.0+ */
49 dev_dbg(pdev->dev, fmt, ##__VA_ARGS__); \
94 #define JSM_VERSION "jsm: 1.2-1-INKERNEL"
95 #define JSM_PARTNUM "40002438_A-INKERNEL"
124 * Per-board information
128 int boardnum; /* Board number: 0-32 */
183 #define RQUEUEMASK 0x1FFF /* 8 K - 1 */
184 #define EQUEUEMASK 0x1FFF /* 8 K - 1 */
221 u8 *ch_rqueue; /* Our read queue buffer - malloc'ed */
225 u8 *ch_equeue; /* Our error queue buffer - malloc'ed */
[all …]
/openbmc/linux/arch/arm/mach-qcom/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
59 node = of_find_compatible_node(NULL, NULL, "qcom,gcc-msm8660"); in scss_release_secondary()
62 return -ENXIO; in scss_release_secondary()
68 return -ENOMEM; in scss_release_secondary()
82 void __iomem *reg; in cortex_a7_release_secondary() local
88 return -ENODEV; in cortex_a7_release_secondary()
92 ret = -ENODEV; in cortex_a7_release_secondary()
96 reg = of_iomap(acc_node, 0); in cortex_a7_release_secondary()
97 if (!reg) { in cortex_a7_release_secondary()
98 ret = -ENOMEM; in cortex_a7_release_secondary()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
42 reg:
54 Bits [11:0] in the reg cell must be set to
57 All other bits in the reg cell must be set to 0.
[all …]
/openbmc/linux/arch/sparc/kernel/
H A Dpci_common.c1 // SPDX-License-Identifier: GPL-2.0
23 unsigned long reg) in config_out_of_range() argument
25 if (bus < pbm->pci_first_busno || in config_out_of_range()
26 bus > pbm->pci_last_busno) in config_out_of_range()
34 unsigned long reg) in sun4u_config_mkaddr() argument
36 unsigned long rbits = pbm->config_space_reg_bits; in sun4u_config_mkaddr()
38 if (config_out_of_range(pbm, bus, devfn, reg)) in sun4u_config_mkaddr()
41 reg = (reg & ((1 << rbits) - 1)); in sun4u_config_mkaddr()
45 return (void *) (pbm->config_space | bus | devfn | reg); in sun4u_config_mkaddr()
50 * Strange but true, and I see no language in the UltraSPARC-IIi
[all …]
/openbmc/linux/sound/pci/cs46xx/
H A Dcs46xx_dsp_scb_types.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
32 31 [30-28]27 [26:24] 23 22 21 20 [19:18] [17:16] 15 14 13 12 11 10 9 8 7 6 [5:0]
35 |H|_____ |H|_________|S_|D |__|__|______|_______|___|ne|__ |__ |__|__|_|_|_|_|_Count -1|
39 u32 saw; /* Source Address Word */ member
44 u32 npaw; /* Next-Page Address Word */
48 31-30 29 28 [27:16] [15:12] [11:3] [2:0]
50 |SV |LE|SE| Sample-end byte offset | | Page-map entry offset for next | |
51 |page|__|__| ___________________________|_________|__page, if !sample-end___________|____|
53 u32 npcw; /* Next-Page Control Word */
54 u32 lbaw; /* Loop-Begin Address Word */
[all …]
/openbmc/linux/drivers/regulator/
H A Dqcom_spmi-regulator.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
8 #include <linux/devm-helpers.h>
57 * struct spmi_regulator_init_data - spmi-regulator initialization data
365 * struct spmi_voltage_range - regulator set point voltage mapping description
380 * (max_uV - min_uV) % step_uV == 0
381 * (set_point_min_uV - min_uV) % step_uV == 0*
382 * (set_point_max_uV - min_uV) % step_uV == 0*
383 * n_voltages = (set_point_max_uV - set_point_min_uV) / step_uV + 1
627 return regmap_bulk_read(vreg->regmap, vreg->base + addr, buf, len); in spmi_vreg_read()
[all …]
/openbmc/linux/drivers/iio/imu/bno055/
H A Dbno055_ser_core.c1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2021-2022 Istituto Italiano di Tecnologia
33 * +------+------+-----+-----+----- ... ----+
34 * | 0xAA | 0xOO | REG | LEN | payload[LEN] |
35 * +------+------+-----+-----+----- ... ----+
38 * +------+----------+
40 * +------+----------+
45 * sw resets - bno055 on serial bus basically requires the hw reset pin).
48 * +------+------+-----+-----+
49 * | 0xAA | 0xO1 | REG | LEN |
[all …]
/openbmc/linux/drivers/soc/qcom/
H A Dspm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
6 * SAW power controller driver
193 enum spm_reg reg, u32 val) in spm_register_write() argument
195 if (drv->reg_data->reg_offset[reg]) in spm_register_write()
196 writel_relaxed(val, drv->reg_base + in spm_register_write()
197 drv->reg_data->reg_offset[reg]); in spm_register_write()
202 enum spm_reg reg, u32 val) in spm_register_write_sync() argument
206 if (!drv->reg_data->reg_offset[reg]) in spm_register_write_sync()
210 writel_relaxed(val, drv->reg_base + in spm_register_write_sync()
[all …]
/openbmc/linux/arch/sparc/include/asm/
H A Dtsb.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * power-of-2 sized table of TAG/PTE pairs. The cpu precomputes
26 * Each 16-byte slot of the TSB is the 8-byte tag and then the 8-byte
30 * -------------------------------------------------
31 * | - | CONTEXT | - | VADDR bits 63:22 |
32 * -------------------------------------------------
35 * But actually, since we use per-mm TSB's, we zero out the CONTEXT
49 #define TSB_TAG_LOCK_HIGH (1 << (TSB_TAG_LOCK_BIT - 32))
52 #define TSB_TAG_INVALID_HIGH (1 << (TSB_TAG_INVALID_BIT - 32))
55 * those if possible so we don't need to hard-lock the TSB mapping
[all …]

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