146680fe9SYassine Oudjana// SPDX-License-Identifier: BSD-3-Clause 246680fe9SYassine Oudjana/* 346680fe9SYassine Oudjana * Copyright (c) 2020, Yassine Oudjana <y.oudjana@protonmail.com> 446680fe9SYassine Oudjana */ 546680fe9SYassine Oudjana 646680fe9SYassine Oudjana#include "pm8994.dtsi" 746680fe9SYassine Oudjana#include "pmi8994.dtsi" 846680fe9SYassine Oudjana#include <dt-bindings/input/input.h> 946680fe9SYassine Oudjana#include <dt-bindings/gpio/gpio.h> 1046680fe9SYassine Oudjana#include <dt-bindings/leds/common.h> 1146680fe9SYassine Oudjana#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 1246680fe9SYassine Oudjana 1346680fe9SYassine Oudjana/ { 1446680fe9SYassine Oudjana divclk1_cdc: divclk1 { 1546680fe9SYassine Oudjana compatible = "gpio-gate-clock"; 1646680fe9SYassine Oudjana clocks = <&rpmcc RPM_SMD_DIV_CLK1>; 1746680fe9SYassine Oudjana #clock-cells = <0>; 1846680fe9SYassine Oudjana enable-gpios = <&pm8994_gpios 15 GPIO_ACTIVE_HIGH>; 1946680fe9SYassine Oudjana 2046680fe9SYassine Oudjana pinctrl-names = "default"; 2146680fe9SYassine Oudjana pinctrl-0 = <&divclk1_default>; 2246680fe9SYassine Oudjana }; 2346680fe9SYassine Oudjana 2446680fe9SYassine Oudjana divclk4: divclk4 { 2546680fe9SYassine Oudjana compatible = "fixed-clock"; 2646680fe9SYassine Oudjana #clock-cells = <0>; 2746680fe9SYassine Oudjana clock-frequency = <32768>; 2846680fe9SYassine Oudjana clock-output-names = "divclk4"; 2946680fe9SYassine Oudjana 3046680fe9SYassine Oudjana pinctrl-names = "default"; 3146680fe9SYassine Oudjana pinctrl-0 = <&divclk4_pin_a>; 3246680fe9SYassine Oudjana }; 3346680fe9SYassine Oudjana 34b08f5cbdSKrzysztof Kozlowski gpio-keys { 3546680fe9SYassine Oudjana compatible = "gpio-keys"; 3646680fe9SYassine Oudjana 37b08f5cbdSKrzysztof Kozlowski key-vol-up { 3846680fe9SYassine Oudjana label = "Volume Up"; 3946680fe9SYassine Oudjana gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; 4046680fe9SYassine Oudjana linux,code = <KEY_VOLUMEUP>; 4146680fe9SYassine Oudjana wakeup-source; 4246680fe9SYassine Oudjana debounce-interval = <15>; 4346680fe9SYassine Oudjana }; 4446680fe9SYassine Oudjana 45b08f5cbdSKrzysztof Kozlowski key-dome { 4646680fe9SYassine Oudjana label = "Home"; 4746680fe9SYassine Oudjana gpios = <&tlmm 34 GPIO_ACTIVE_LOW>; 4846680fe9SYassine Oudjana linux,code = <KEY_HOME>; 4946680fe9SYassine Oudjana wakeup-source; 5046680fe9SYassine Oudjana debounce-interval = <15>; 5146680fe9SYassine Oudjana }; 5246680fe9SYassine Oudjana }; 5346680fe9SYassine Oudjana 54d710fdfeSYassine Oudjana irled { 55d710fdfeSYassine Oudjana compatible = "pwm-ir-tx"; 56d710fdfeSYassine Oudjana pwms = <&pm8994_lpg 1 1000000>; 57d710fdfeSYassine Oudjana 58d710fdfeSYassine Oudjana pinctrl-names = "default"; 59d710fdfeSYassine Oudjana pinctrl-0 = <&irled_default>; 60d710fdfeSYassine Oudjana }; 61d710fdfeSYassine Oudjana 6246680fe9SYassine Oudjana reserved-memory { 6346680fe9SYassine Oudjana memory@88800000 { 6446680fe9SYassine Oudjana reg = <0x0 0x88800000 0x0 0x1400000>; 6546680fe9SYassine Oudjana no-map; 6646680fe9SYassine Oudjana }; 6746680fe9SYassine Oudjana 6846680fe9SYassine Oudjana /* This platform has all PIL regions offset by 0x1400000 */ 6946680fe9SYassine Oudjana /delete-node/ mpss@88800000; 70902d97a4SYassine Oudjana mpss_mem: mpss@89c00000 { 7146680fe9SYassine Oudjana reg = <0x0 0x89c00000 0x0 0x6200000>; 7246680fe9SYassine Oudjana no-map; 7346680fe9SYassine Oudjana }; 7446680fe9SYassine Oudjana 7546680fe9SYassine Oudjana /delete-node/ adsp@8ea00000; 76902d97a4SYassine Oudjana adsp_mem: adsp@8fe00000 { 7746680fe9SYassine Oudjana reg = <0x0 0x8fe00000 0x0 0x1b00000>; 7846680fe9SYassine Oudjana no-map; 7946680fe9SYassine Oudjana }; 8046680fe9SYassine Oudjana 81902d97a4SYassine Oudjana /delete-node/ slpi@90500000; 82902d97a4SYassine Oudjana slpi_mem: slpi@91900000 { 8346680fe9SYassine Oudjana reg = <0x0 0x91900000 0x0 0xa00000>; 8446680fe9SYassine Oudjana no-map; 8546680fe9SYassine Oudjana }; 8646680fe9SYassine Oudjana 87902d97a4SYassine Oudjana /delete-node/ gpu@90f00000; 88902d97a4SYassine Oudjana gpu_mem: gpu@92300000 { 8946680fe9SYassine Oudjana compatible = "shared-dma-pool"; 9046680fe9SYassine Oudjana reg = <0x0 0x92300000 0x0 0x2000>; 9146680fe9SYassine Oudjana no-map; 9246680fe9SYassine Oudjana }; 9346680fe9SYassine Oudjana 9446680fe9SYassine Oudjana /delete-node/ venus@91000000; 95902d97a4SYassine Oudjana venus_mem: venus@92400000 { 9646680fe9SYassine Oudjana reg = <0x0 0x92400000 0x0 0x500000>; 9746680fe9SYassine Oudjana no-map; 9846680fe9SYassine Oudjana }; 9946680fe9SYassine Oudjana 10046680fe9SYassine Oudjana ramoops@92900000 { 10146680fe9SYassine Oudjana compatible = "ramoops"; 10246680fe9SYassine Oudjana reg = <0x0 0x92900000 0x0 0x100000>; 10346680fe9SYassine Oudjana no-map; 10446680fe9SYassine Oudjana 10546680fe9SYassine Oudjana record-size = <0x8000>; 10646680fe9SYassine Oudjana console-size = <0x80000>; 10746680fe9SYassine Oudjana ftrace-size = <0x20000>; 10846680fe9SYassine Oudjana pmsg-size = <0x40000>; 10946680fe9SYassine Oudjana }; 11046680fe9SYassine Oudjana 111902d97a4SYassine Oudjana /delete-node/ rmtfs; 11246680fe9SYassine Oudjana rmtfs@f6c00000 { 11346680fe9SYassine Oudjana compatible = "qcom,rmtfs-mem"; 11446680fe9SYassine Oudjana reg = <0 0xf6c00000 0 0x200000>; 11546680fe9SYassine Oudjana no-map; 11646680fe9SYassine Oudjana 11746680fe9SYassine Oudjana qcom,client-id = <1>; 11846680fe9SYassine Oudjana qcom,vmid = <15>; 11946680fe9SYassine Oudjana }; 12046680fe9SYassine Oudjana 12146680fe9SYassine Oudjana /delete-node/ mba@91500000; 122902d97a4SYassine Oudjana mba_mem: mba@f6f00000 { 12346680fe9SYassine Oudjana reg = <0x0 0xf6f00000 0x0 0x100000>; 12446680fe9SYassine Oudjana no-map; 12546680fe9SYassine Oudjana }; 12646680fe9SYassine Oudjana }; 12746680fe9SYassine Oudjana 12846680fe9SYassine Oudjana vph_pwr: vph-pwr-regulator { 12946680fe9SYassine Oudjana compatible = "regulator-fixed"; 13046680fe9SYassine Oudjana regulator-name = "vph_pwr"; 13146680fe9SYassine Oudjana regulator-min-microvolt = <3800000>; 13246680fe9SYassine Oudjana regulator-max-microvolt = <3800000>; 13346680fe9SYassine Oudjana regulator-always-on; 13446680fe9SYassine Oudjana regulator-boot-on; 13546680fe9SYassine Oudjana }; 13646680fe9SYassine Oudjana 13746680fe9SYassine Oudjana vdd_3v2_tp: vdd-3v2-tp { 13846680fe9SYassine Oudjana compatible = "regulator-fixed"; 13946680fe9SYassine Oudjana regulator-name = "vdd_3v2_tp"; 14046680fe9SYassine Oudjana regulator-min-microvolt = <3200000>; 14146680fe9SYassine Oudjana regulator-max-microvolt = <3200000>; 14246680fe9SYassine Oudjana startup-delay-us = <4000>; 14346680fe9SYassine Oudjana vin-supply = <&vph_pwr>; 14446680fe9SYassine Oudjana 14546680fe9SYassine Oudjana gpio = <&tlmm 73 0>; 14646680fe9SYassine Oudjana enable-active-high; 14746680fe9SYassine Oudjana }; 14846680fe9SYassine Oudjana 14946680fe9SYassine Oudjana vdd_3v3: rome-vreg { 15046680fe9SYassine Oudjana compatible = "regulator-fixed"; 15146680fe9SYassine Oudjana regulator-name = "vdd_3v3"; 15246680fe9SYassine Oudjana regulator-min-microvolt = <3300000>; 15346680fe9SYassine Oudjana regulator-max-microvolt = <3300000>; 15446680fe9SYassine Oudjana startup-delay-us = <4000>; 15546680fe9SYassine Oudjana vin-supply = <&vph_pwr_bbyp>; 15646680fe9SYassine Oudjana 15746680fe9SYassine Oudjana gpio = <&pm8994_gpios 9 0>; 15846680fe9SYassine Oudjana enable-active-high; 15946680fe9SYassine Oudjana pinctrl-names = "default"; 16046680fe9SYassine Oudjana pinctrl-0 = <&rome_enable_default>; 16146680fe9SYassine Oudjana 16246680fe9SYassine Oudjana /* Required by QCA6174a - vddpe-3v3 */ 16346680fe9SYassine Oudjana regulator-always-on; 16446680fe9SYassine Oudjana }; 16546680fe9SYassine Oudjana 16646680fe9SYassine Oudjana /* WL_EN pin defined as a fixed regulator */ 16746680fe9SYassine Oudjana wlan_en: wlan-en-1-8v { 16846680fe9SYassine Oudjana compatible = "regulator-fixed"; 16946680fe9SYassine Oudjana regulator-name = "wlan-en-regulator"; 17046680fe9SYassine Oudjana regulator-min-microvolt = <1800000>; 17146680fe9SYassine Oudjana regulator-max-microvolt = <1800000>; 17246680fe9SYassine Oudjana 17346680fe9SYassine Oudjana gpio = <&pm8994_gpios 8 0>; 17446680fe9SYassine Oudjana /* WLAN card specific delay */ 17546680fe9SYassine Oudjana startup-delay-us = <70000>; 17646680fe9SYassine Oudjana enable-active-high; 17746680fe9SYassine Oudjana pinctrl-names = "default"; 17846680fe9SYassine Oudjana pinctrl-0 = <&wlan_en_default>; 17946680fe9SYassine Oudjana }; 18046680fe9SYassine Oudjana}; 18146680fe9SYassine Oudjana 18246680fe9SYassine Oudjana&adsp_pil { 18346680fe9SYassine Oudjana status = "okay"; 18446680fe9SYassine Oudjana}; 18546680fe9SYassine Oudjana 18646680fe9SYassine Oudjana&blsp2_i2c2 { 18746680fe9SYassine Oudjana status = "okay"; 188bb270c86SKrzysztof Kozlowski clock-frequency = <400000>; 18946680fe9SYassine Oudjana 190*f7eb4542SKrzysztof Kozlowski nfc: nfc@28 { 19146680fe9SYassine Oudjana compatible = "nxp,nxp-nci-i2c"; 19246680fe9SYassine Oudjana 19346680fe9SYassine Oudjana reg = <0x28>; 19446680fe9SYassine Oudjana 19546680fe9SYassine Oudjana interrupt-parent = <&tlmm>; 19646680fe9SYassine Oudjana interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 19746680fe9SYassine Oudjana 19846680fe9SYassine Oudjana enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; 19946680fe9SYassine Oudjana firmware-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; 20046680fe9SYassine Oudjana 20146680fe9SYassine Oudjana pinctrl-names = "default"; 20246680fe9SYassine Oudjana pinctrl-0 = <&nfc_default>; 20346680fe9SYassine Oudjana }; 20446680fe9SYassine Oudjana}; 20546680fe9SYassine Oudjana 20646680fe9SYassine Oudjana&blsp2_i2c3 { 20746680fe9SYassine Oudjana status = "okay"; 20846680fe9SYassine Oudjana 209*f7eb4542SKrzysztof Kozlowski typec: typec@47 { 210de0a2ae3SYassine Oudjana compatible = "ti,tusb320l"; 21146680fe9SYassine Oudjana reg = <0x47>; 21246680fe9SYassine Oudjana interrupt-parent = <&tlmm>; 21346680fe9SYassine Oudjana interrupts = <63 IRQ_TYPE_EDGE_RISING>; 21446680fe9SYassine Oudjana }; 21546680fe9SYassine Oudjana}; 21646680fe9SYassine Oudjana 21746680fe9SYassine Oudjana&blsp2_i2c6 { 21846680fe9SYassine Oudjana status = "okay"; 219368f8d19SKrzysztof Kozlowski /* MSM_TS */ 22046680fe9SYassine Oudjana}; 22146680fe9SYassine Oudjana 22246680fe9SYassine Oudjana&blsp1_uart2 { 22346680fe9SYassine Oudjana status = "okay"; 22446680fe9SYassine Oudjana label = "QCA_UART"; 22546680fe9SYassine Oudjana 226f7aaaf30SKrzysztof Kozlowski bluetooth: bluetooth { 22746680fe9SYassine Oudjana compatible = "qcom,qca6174-bt"; 22846680fe9SYassine Oudjana 22946680fe9SYassine Oudjana enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>; 23046680fe9SYassine Oudjana clocks = <&divclk4>; 23146680fe9SYassine Oudjana }; 23246680fe9SYassine Oudjana}; 23346680fe9SYassine Oudjana 2348b764ed0SDmitry Baryshkov&gpu { 2358b764ed0SDmitry Baryshkov status = "okay"; 2368b764ed0SDmitry Baryshkov}; 2378b764ed0SDmitry Baryshkov 2388b764ed0SDmitry Baryshkov&mdss { 2398b764ed0SDmitry Baryshkov status = "okay"; 2408b764ed0SDmitry Baryshkov}; 2418b764ed0SDmitry Baryshkov 2428b764ed0SDmitry Baryshkov&mdss_dsi0 { 24346680fe9SYassine Oudjana status = "okay"; 24446680fe9SYassine Oudjana 24546680fe9SYassine Oudjana vdd-supply = <&vreg_l2a_1p25>; 24646680fe9SYassine Oudjana vddio-supply = <&vreg_l14a_1p8>; 24746680fe9SYassine Oudjana 24846680fe9SYassine Oudjana pinctrl-names = "default", "sleep"; 24946680fe9SYassine Oudjana pinctrl-0 = <&mdss_dsi_default &mdss_te_default>; 25046680fe9SYassine Oudjana pinctrl-1 = <&mdss_dsi_sleep &mdss_te_sleep>; 25146680fe9SYassine Oudjana}; 25246680fe9SYassine Oudjana 2538b764ed0SDmitry Baryshkov&mdss_dsi0_out { 25446680fe9SYassine Oudjana status = "okay"; 25546680fe9SYassine Oudjana 25646680fe9SYassine Oudjana data-lanes = <0 1 2 3>; 25746680fe9SYassine Oudjana}; 25846680fe9SYassine Oudjana 2598b764ed0SDmitry Baryshkov&mdss_dsi0_phy { 26046680fe9SYassine Oudjana status = "okay"; 26146680fe9SYassine Oudjana 26246680fe9SYassine Oudjana vcca-supply = <&vreg_l28a_0p925>; 26346680fe9SYassine Oudjana}; 26446680fe9SYassine Oudjana 26546680fe9SYassine Oudjana&mmcc { 26646680fe9SYassine Oudjana vdd-gfx-supply = <&vdd_gfx>; 26746680fe9SYassine Oudjana}; 26846680fe9SYassine Oudjana 26973f7731bSYassine Oudjana&mss_pil { 27073f7731bSYassine Oudjana status = "okay"; 27173f7731bSYassine Oudjana 27273f7731bSYassine Oudjana pll-supply = <&vreg_l12a_1p8>; 27373f7731bSYassine Oudjana}; 27473f7731bSYassine Oudjana 27546680fe9SYassine Oudjana&pcie0 { 27646680fe9SYassine Oudjana status = "okay"; 27746680fe9SYassine Oudjana 27846680fe9SYassine Oudjana /* Supplied by vdd_3v3, but choose wlan_en to drive enable pin high */ 27946680fe9SYassine Oudjana vddpe-3v3-supply = <&wlan_en>; 28046680fe9SYassine Oudjana vdda-supply = <&vreg_l28a_0p925>; 28146680fe9SYassine Oudjana 28246680fe9SYassine Oudjana perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; 28346680fe9SYassine Oudjana wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; 28446680fe9SYassine Oudjana}; 28546680fe9SYassine Oudjana 28646680fe9SYassine Oudjana&pcie_phy { 28746680fe9SYassine Oudjana status = "okay"; 28846680fe9SYassine Oudjana 28946680fe9SYassine Oudjana vdda-phy-supply = <&vreg_l28a_0p925>; 29046680fe9SYassine Oudjana vdda-pll-supply = <&vreg_l12a_1p8>; 29146680fe9SYassine Oudjana}; 29246680fe9SYassine Oudjana 29346680fe9SYassine Oudjana&pm8994_resin { 29446680fe9SYassine Oudjana status = "okay"; 29546680fe9SYassine Oudjana 29646680fe9SYassine Oudjana linux,code = <KEY_VOLUMEDOWN>; 29746680fe9SYassine Oudjana}; 29846680fe9SYassine Oudjana 299d710fdfeSYassine Oudjana&pm8994_lpg { 300d710fdfeSYassine Oudjana status = "okay"; 301d710fdfeSYassine Oudjana 302d710fdfeSYassine Oudjana qcom,power-source = <1>; 303d710fdfeSYassine Oudjana}; 304d710fdfeSYassine Oudjana 305d710fdfeSYassine Oudjana&pmi8994_lpg { 306d710fdfeSYassine Oudjana status = "okay"; 307d710fdfeSYassine Oudjana 308d710fdfeSYassine Oudjana qcom,power-source = <1>; 309d710fdfeSYassine Oudjana 310d710fdfeSYassine Oudjana multi-led { 311d710fdfeSYassine Oudjana color = <LED_COLOR_ID_RGB>; 312d710fdfeSYassine Oudjana function = LED_FUNCTION_STATUS; 313d710fdfeSYassine Oudjana 314d710fdfeSYassine Oudjana #address-cells = <1>; 315d710fdfeSYassine Oudjana #size-cells = <0>; 316d710fdfeSYassine Oudjana 317d710fdfeSYassine Oudjana led@1 { 318d710fdfeSYassine Oudjana reg = <1>; 319d710fdfeSYassine Oudjana color = <LED_COLOR_ID_BLUE>; 320d710fdfeSYassine Oudjana }; 321d710fdfeSYassine Oudjana 322d710fdfeSYassine Oudjana led@2 { 323d710fdfeSYassine Oudjana reg = <2>; 324d710fdfeSYassine Oudjana color = <LED_COLOR_ID_GREEN>; 325d710fdfeSYassine Oudjana }; 326d710fdfeSYassine Oudjana 327d710fdfeSYassine Oudjana led@3 { 328d710fdfeSYassine Oudjana reg = <3>; 329d710fdfeSYassine Oudjana color = <LED_COLOR_ID_RED>; 330d710fdfeSYassine Oudjana }; 331d710fdfeSYassine Oudjana }; 332d710fdfeSYassine Oudjana}; 333d710fdfeSYassine Oudjana 3345a1816ccSKrzysztof Kozlowski&slim_msm { 3355a1816ccSKrzysztof Kozlowski status = "okay"; 3365a1816ccSKrzysztof Kozlowski 3375a1816ccSKrzysztof Kozlowski slim@1 { 3385a1816ccSKrzysztof Kozlowski reg = <1>; 3395a1816ccSKrzysztof Kozlowski #address-cells = <2>; 3405a1816ccSKrzysztof Kozlowski #size-cells = <0>; 3415a1816ccSKrzysztof Kozlowski 3425a1816ccSKrzysztof Kozlowski tasha_ifd: tas-ifd@0,0 { 3435a1816ccSKrzysztof Kozlowski compatible = "slim217,1a0"; 3445a1816ccSKrzysztof Kozlowski reg = <0 0>; 3455a1816ccSKrzysztof Kozlowski }; 3465a1816ccSKrzysztof Kozlowski 3475a1816ccSKrzysztof Kozlowski wcd9335: codec@1,0 { 3485a1816ccSKrzysztof Kozlowski compatible = "slim217,1a0"; 3495a1816ccSKrzysztof Kozlowski reg = <1 0>; 3505a1816ccSKrzysztof Kozlowski 3515a1816ccSKrzysztof Kozlowski clock-names = "mclk", "slimbus"; 3525a1816ccSKrzysztof Kozlowski clocks = <&divclk1_cdc>, 3535a1816ccSKrzysztof Kozlowski <&rpmcc RPM_SMD_BB_CLK1>; 3545a1816ccSKrzysztof Kozlowski interrupt-parent = <&tlmm>; 3555a1816ccSKrzysztof Kozlowski interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, 3565a1816ccSKrzysztof Kozlowski <53 IRQ_TYPE_LEVEL_HIGH>; 3575a1816ccSKrzysztof Kozlowski interrupt-names = "intr1", "intr2"; 3585a1816ccSKrzysztof Kozlowski interrupt-controller; 3595a1816ccSKrzysztof Kozlowski #interrupt-cells = <1>; 3605a1816ccSKrzysztof Kozlowski 3615a1816ccSKrzysztof Kozlowski pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; 3625a1816ccSKrzysztof Kozlowski pinctrl-names = "default"; 3635a1816ccSKrzysztof Kozlowski 3645a1816ccSKrzysztof Kozlowski reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; 3655a1816ccSKrzysztof Kozlowski slim-ifc-dev = <&tasha_ifd>; 3665a1816ccSKrzysztof Kozlowski 3675a1816ccSKrzysztof Kozlowski #sound-dai-cells = <1>; 3685a1816ccSKrzysztof Kozlowski 3695a1816ccSKrzysztof Kozlowski vdd-buck-supply = <&vreg_s4a_1p8>; 3705a1816ccSKrzysztof Kozlowski vdd-buck-sido-supply = <&vreg_s4a_1p8>; 3715a1816ccSKrzysztof Kozlowski vdd-rx-supply = <&vreg_s4a_1p8>; 3725a1816ccSKrzysztof Kozlowski vdd-tx-supply = <&vreg_s4a_1p8>; 3735a1816ccSKrzysztof Kozlowski vdd-vbat-supply = <&vph_pwr>; 3745a1816ccSKrzysztof Kozlowski vdd-micbias-supply = <&vph_pwr_bbyp>; 3755a1816ccSKrzysztof Kozlowski vdd-io-supply = <&vreg_s4a_1p8>; 3765a1816ccSKrzysztof Kozlowski }; 3775a1816ccSKrzysztof Kozlowski }; 3785a1816ccSKrzysztof Kozlowski}; 3795a1816ccSKrzysztof Kozlowski 38073f7731bSYassine Oudjana&slpi_pil { 38173f7731bSYassine Oudjana status = "okay"; 38273f7731bSYassine Oudjana 38373f7731bSYassine Oudjana px-supply = <&vreg_lvs2a_1p8>; 38473f7731bSYassine Oudjana}; 38573f7731bSYassine Oudjana 38646680fe9SYassine Oudjana&usb3 { 38746680fe9SYassine Oudjana status = "okay"; 38846680fe9SYassine Oudjana extcon = <&typec>; 38946680fe9SYassine Oudjana 39046680fe9SYassine Oudjana qcom,select-utmi-as-pipe-clk; 391b77a1c4dSKrzysztof Kozlowski}; 39246680fe9SYassine Oudjana 393b77a1c4dSKrzysztof Kozlowski&usb3_dwc3 { 39446680fe9SYassine Oudjana extcon = <&typec>; 39546680fe9SYassine Oudjana 39646680fe9SYassine Oudjana /* usb3-phy is not used on this device */ 39746680fe9SYassine Oudjana phys = <&hsusb_phy1>; 39846680fe9SYassine Oudjana phy-names = "usb2-phy"; 39946680fe9SYassine Oudjana 40046680fe9SYassine Oudjana maximum-speed = "high-speed"; 40146680fe9SYassine Oudjana snps,is-utmi-l1-suspend; 40246680fe9SYassine Oudjana snps,usb2-gadget-lpm-disable; 40346680fe9SYassine Oudjana snps,hird-threshold = /bits/ 8 <0>; 40446680fe9SYassine Oudjana}; 40546680fe9SYassine Oudjana 40646680fe9SYassine Oudjana&hsusb_phy1 { 40746680fe9SYassine Oudjana status = "okay"; 40846680fe9SYassine Oudjana 40946680fe9SYassine Oudjana vdda-pll-supply = <&vreg_l12a_1p8>; 41046680fe9SYassine Oudjana vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; 41146680fe9SYassine Oudjana}; 41246680fe9SYassine Oudjana 41346680fe9SYassine Oudjana&ufshc { 41446680fe9SYassine Oudjana status = "okay"; 41546680fe9SYassine Oudjana 41646680fe9SYassine Oudjana vcc-supply = <&vreg_l20a_2p95>; 41746680fe9SYassine Oudjana vccq-supply = <&vreg_l25a_1p2>; 41846680fe9SYassine Oudjana vccq2-supply = <&vreg_s4a_1p8>; 41946680fe9SYassine Oudjana 42046680fe9SYassine Oudjana vcc-max-microamp = <600000>; 42146680fe9SYassine Oudjana vccq-max-microamp = <450000>; 42246680fe9SYassine Oudjana vccq2-max-microamp = <450000>; 42346680fe9SYassine Oudjana}; 42446680fe9SYassine Oudjana 42546680fe9SYassine Oudjana&ufsphy { 42646680fe9SYassine Oudjana status = "okay"; 42746680fe9SYassine Oudjana 42846680fe9SYassine Oudjana vdda-phy-supply = <&vreg_l28a_0p925>; 42946680fe9SYassine Oudjana vdda-pll-supply = <&vreg_l12a_1p8>; 43046680fe9SYassine Oudjana vddp-ref-clk-supply = <&vreg_l25a_1p2>; 43146680fe9SYassine Oudjana}; 43246680fe9SYassine Oudjana 43346680fe9SYassine Oudjana&venus { 43446680fe9SYassine Oudjana status = "okay"; 43546680fe9SYassine Oudjana}; 43646680fe9SYassine Oudjana 43746680fe9SYassine Oudjana&rpm_requests { 438372698e8SKrzysztof Kozlowski regulators-0 { 43946680fe9SYassine Oudjana compatible = "qcom,rpm-pm8994-regulators"; 44046680fe9SYassine Oudjana 44146680fe9SYassine Oudjana vdd_s1-supply = <&vph_pwr>; 44246680fe9SYassine Oudjana vdd_s2-supply = <&vph_pwr>; 44346680fe9SYassine Oudjana vdd_s3-supply = <&vph_pwr>; 44446680fe9SYassine Oudjana vdd_s4-supply = <&vph_pwr>; 44546680fe9SYassine Oudjana vdd_s5-supply = <&vph_pwr>; 44646680fe9SYassine Oudjana vdd_s6-supply = <&vph_pwr>; 44746680fe9SYassine Oudjana vdd_s7-supply = <&vph_pwr>; 44846680fe9SYassine Oudjana vdd_s8-supply = <&vph_pwr>; 44946680fe9SYassine Oudjana vdd_s9-supply = <&vph_pwr>; 45046680fe9SYassine Oudjana vdd_s10-supply = <&vph_pwr>; 45146680fe9SYassine Oudjana vdd_s11-supply = <&vph_pwr>; 45246680fe9SYassine Oudjana vdd_s12-supply = <&vph_pwr>; 45346680fe9SYassine Oudjana vdd_l1-supply = <&vreg_s1b_1p025>; 45446680fe9SYassine Oudjana vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>; 45546680fe9SYassine Oudjana vdd_l3_l11-supply = <&vreg_s3a_1p3>; 45646680fe9SYassine Oudjana vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>; 45746680fe9SYassine Oudjana vdd_l5_l7-supply = <&vreg_s5a_2p15>; 45846680fe9SYassine Oudjana vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>; 45946680fe9SYassine Oudjana vdd_l8_l16_l30-supply = <&vph_pwr>; 46046680fe9SYassine Oudjana vdd_l9_l10_l18_l22-supply = <&vph_pwr_bbyp>; 46146680fe9SYassine Oudjana vdd_l13_l19_l23_l24-supply = <&vph_pwr_bbyp>; 46246680fe9SYassine Oudjana vdd_l14_l15-supply = <&vreg_s5a_2p15>; 46346680fe9SYassine Oudjana vdd_l17_l29-supply = <&vph_pwr_bbyp>; 46446680fe9SYassine Oudjana vdd_l20_l21-supply = <&vph_pwr_bbyp>; 46546680fe9SYassine Oudjana vdd_l25-supply = <&vreg_s3a_1p3>; 46646680fe9SYassine Oudjana vdd_lvs1_2-supply = <&vreg_s4a_1p8>; 46746680fe9SYassine Oudjana 46846680fe9SYassine Oudjana vreg_s3a_1p3: s3 { 46946680fe9SYassine Oudjana regulator-name = "vreg_s3a_1p3"; 47046680fe9SYassine Oudjana regulator-min-microvolt = <1300000>; 47146680fe9SYassine Oudjana regulator-max-microvolt = <1300000>; 47246680fe9SYassine Oudjana 47346680fe9SYassine Oudjana /* Required by QCA6174a - vdd-core */ 47446680fe9SYassine Oudjana regulator-always-on; 47546680fe9SYassine Oudjana }; 47646680fe9SYassine Oudjana vreg_s4a_1p8: s4 { 47746680fe9SYassine Oudjana regulator-name = "vreg_s4a_1p8"; 47846680fe9SYassine Oudjana regulator-min-microvolt = <1800000>; 47946680fe9SYassine Oudjana regulator-max-microvolt = <1800000>; 48046680fe9SYassine Oudjana regulator-allow-set-load; 48146680fe9SYassine Oudjana 48246680fe9SYassine Oudjana /* Required by QCA6174a - vddio */ 48346680fe9SYassine Oudjana regulator-always-on; 48446680fe9SYassine Oudjana }; 48546680fe9SYassine Oudjana vreg_s5a_2p15: s5 { 48646680fe9SYassine Oudjana regulator-name = "vreg_s5a_2p15"; 48746680fe9SYassine Oudjana regulator-min-microvolt = <2150000>; 48846680fe9SYassine Oudjana regulator-max-microvolt = <2150000>; 48946680fe9SYassine Oudjana }; 49046680fe9SYassine Oudjana vreg_s7a_0p8: s7 { 49146680fe9SYassine Oudjana regulator-name = "vreg_s7a_0p8"; 49246680fe9SYassine Oudjana regulator-min-microvolt = <800000>; 49346680fe9SYassine Oudjana regulator-max-microvolt = <800000>; 49446680fe9SYassine Oudjana }; 49546680fe9SYassine Oudjana vreg_l1a_1p0: l1 { 49646680fe9SYassine Oudjana regulator-name = "vreg_l1a_1p0"; 49746680fe9SYassine Oudjana regulator-min-microvolt = <1000000>; 49846680fe9SYassine Oudjana regulator-max-microvolt = <1000000>; 49946680fe9SYassine Oudjana }; 50046680fe9SYassine Oudjana vreg_l2a_1p25: l2 { 50146680fe9SYassine Oudjana regulator-name = "vreg_l2a_1p25"; 50246680fe9SYassine Oudjana regulator-min-microvolt = <1250000>; 50346680fe9SYassine Oudjana regulator-max-microvolt = <1250000>; 50446680fe9SYassine Oudjana }; 50546680fe9SYassine Oudjana vreg_l4a_1p225: l4 { 50646680fe9SYassine Oudjana regulator-name = "vreg_l4a_1p225"; 50746680fe9SYassine Oudjana regulator-min-microvolt = <1225000>; 50846680fe9SYassine Oudjana regulator-max-microvolt = <1225000>; 50946680fe9SYassine Oudjana }; 51046680fe9SYassine Oudjana vreg_l6a_1p8: l6 { 51146680fe9SYassine Oudjana regulator-name = "vreg_l6a_1p8"; 51246680fe9SYassine Oudjana regulator-min-microvolt = <1800000>; 51346680fe9SYassine Oudjana regulator-max-microvolt = <1800000>; 51446680fe9SYassine Oudjana }; 51546680fe9SYassine Oudjana vreg_l8a_1p8: l8 { 51646680fe9SYassine Oudjana regulator-name = "vreg_l8a_1p8"; 51746680fe9SYassine Oudjana regulator-min-microvolt = <1800000>; 51846680fe9SYassine Oudjana regulator-max-microvolt = <1800000>; 51946680fe9SYassine Oudjana }; 52046680fe9SYassine Oudjana vreg_l9a_1p8: l9 { 52146680fe9SYassine Oudjana regulator-name = "vreg_l9a_1p8"; 52246680fe9SYassine Oudjana regulator-min-microvolt = <1800000>; 52346680fe9SYassine Oudjana regulator-max-microvolt = <1800000>; 52446680fe9SYassine Oudjana }; 52546680fe9SYassine Oudjana vreg_l10a_1p8: l10 { 52646680fe9SYassine Oudjana regulator-name = "vreg_l10a_1p8"; 52746680fe9SYassine Oudjana regulator-min-microvolt = <1800000>; 52846680fe9SYassine Oudjana regulator-max-microvolt = <1800000>; 52946680fe9SYassine Oudjana }; 53046680fe9SYassine Oudjana vreg_l12a_1p8: l12 { 53146680fe9SYassine Oudjana regulator-name = "vreg_l12a_1p8"; 53246680fe9SYassine Oudjana regulator-min-microvolt = <1800000>; 53346680fe9SYassine Oudjana regulator-max-microvolt = <1800000>; 53446680fe9SYassine Oudjana regulator-allow-set-load; 53546680fe9SYassine Oudjana }; 53646680fe9SYassine Oudjana vreg_l13a_2p95: l13 { 53746680fe9SYassine Oudjana regulator-name = "vreg_l13a_2p95"; 53846680fe9SYassine Oudjana regulator-min-microvolt = <1800000>; 53946680fe9SYassine Oudjana regulator-max-microvolt = <2950000>; 54046680fe9SYassine Oudjana }; 54146680fe9SYassine Oudjana vreg_l14a_1p8: l14 { 54246680fe9SYassine Oudjana regulator-name = "vreg_l14a_1p8"; 54346680fe9SYassine Oudjana regulator-min-microvolt = <1800000>; 54446680fe9SYassine Oudjana regulator-max-microvolt = <1800000>; 54546680fe9SYassine Oudjana }; 54646680fe9SYassine Oudjana vreg_l15a_1p8: l15 { 54746680fe9SYassine Oudjana regulator-name = "vreg_l15a_1p8"; 54846680fe9SYassine Oudjana regulator-min-microvolt = <1800000>; 54946680fe9SYassine Oudjana regulator-max-microvolt = <1800000>; 55046680fe9SYassine Oudjana }; 55146680fe9SYassine Oudjana vreg_l16a_2p7: l16 { 55246680fe9SYassine Oudjana regulator-name = "vreg_l16a_2p7"; 55346680fe9SYassine Oudjana regulator-min-microvolt = <2700000>; 55446680fe9SYassine Oudjana regulator-max-microvolt = <2700000>; 55546680fe9SYassine Oudjana }; 55646680fe9SYassine Oudjana vreg_l19a_3p3: l19 { 55746680fe9SYassine Oudjana regulator-name = "vreg_l19a_3p3"; 55846680fe9SYassine Oudjana regulator-min-microvolt = <3000000>; 55946680fe9SYassine Oudjana regulator-max-microvolt = <3000000>; 56046680fe9SYassine Oudjana }; 56146680fe9SYassine Oudjana vreg_l20a_2p95: l20 { 56246680fe9SYassine Oudjana regulator-name = "vreg_l20a_2p95"; 56346680fe9SYassine Oudjana regulator-min-microvolt = <2950000>; 56446680fe9SYassine Oudjana regulator-max-microvolt = <2950000>; 56546680fe9SYassine Oudjana regulator-allow-set-load; 56646680fe9SYassine Oudjana }; 56746680fe9SYassine Oudjana vreg_l21a_2p95: l21 { 56846680fe9SYassine Oudjana regulator-name = "vreg_l21a_2p95"; 56946680fe9SYassine Oudjana regulator-min-microvolt = <3300000>; 57046680fe9SYassine Oudjana regulator-max-microvolt = <3300000>; 57146680fe9SYassine Oudjana regulator-always-on; 57246680fe9SYassine Oudjana }; 57346680fe9SYassine Oudjana vreg_l23a_2p8: l23 { 57446680fe9SYassine Oudjana regulator-name = "vreg_l23a_2p8"; 57546680fe9SYassine Oudjana regulator-min-microvolt = <2800000>; 57646680fe9SYassine Oudjana regulator-max-microvolt = <2800000>; 57746680fe9SYassine Oudjana }; 57846680fe9SYassine Oudjana vreg_l24a_3p075: l24 { 57946680fe9SYassine Oudjana regulator-name = "vreg_l24a_3p075"; 58046680fe9SYassine Oudjana regulator-min-microvolt = <3075000>; 58146680fe9SYassine Oudjana regulator-max-microvolt = <3075000>; 58246680fe9SYassine Oudjana }; 58346680fe9SYassine Oudjana vreg_l25a_1p2: l25 { 58446680fe9SYassine Oudjana regulator-name = "vreg_l25a_1p2"; 58546680fe9SYassine Oudjana regulator-min-microvolt = <1200000>; 58646680fe9SYassine Oudjana regulator-max-microvolt = <1200000>; 58746680fe9SYassine Oudjana regulator-allow-set-load; 58846680fe9SYassine Oudjana }; 58946680fe9SYassine Oudjana vreg_l27a_1p2: l27 { 59046680fe9SYassine Oudjana regulator-name = "vreg_l27a_1p2"; 59146680fe9SYassine Oudjana regulator-min-microvolt = <1200000>; 59246680fe9SYassine Oudjana regulator-max-microvolt = <1200000>; 59346680fe9SYassine Oudjana }; 59446680fe9SYassine Oudjana vreg_l28a_0p925: l28 { 59546680fe9SYassine Oudjana regulator-name = "vreg_l28a_0p925"; 59646680fe9SYassine Oudjana regulator-min-microvolt = <925000>; 59746680fe9SYassine Oudjana regulator-max-microvolt = <925000>; 59846680fe9SYassine Oudjana regulator-allow-set-load; 59946680fe9SYassine Oudjana }; 60046680fe9SYassine Oudjana vreg_l30a_1p8: l30 { 60146680fe9SYassine Oudjana regulator-name = "vreg_l30a_1p8"; 60246680fe9SYassine Oudjana regulator-min-microvolt = <1800000>; 60346680fe9SYassine Oudjana regulator-max-microvolt = <1800000>; 60446680fe9SYassine Oudjana 60546680fe9SYassine Oudjana /* Required by QCA6174a - vddio-xtal */ 60646680fe9SYassine Oudjana regulator-always-on; 60746680fe9SYassine Oudjana }; 60846680fe9SYassine Oudjana vreg_l32a_1p8: l32 { 60946680fe9SYassine Oudjana regulator-name = "vreg_l32a_1p8"; 61046680fe9SYassine Oudjana regulator-min-microvolt = <1800000>; 61146680fe9SYassine Oudjana regulator-max-microvolt = <1800000>; 61246680fe9SYassine Oudjana }; 61346680fe9SYassine Oudjana vreg_lvs1a_1p8: lvs1 { 61446680fe9SYassine Oudjana regulator-min-microvolt = <1800000>; 61546680fe9SYassine Oudjana regulator-max-microvolt = <1800000>; 61646680fe9SYassine Oudjana }; 61746680fe9SYassine Oudjana vreg_lvs2a_1p8: lvs2 { 61846680fe9SYassine Oudjana regulator-min-microvolt = <1800000>; 61946680fe9SYassine Oudjana regulator-max-microvolt = <1800000>; 62046680fe9SYassine Oudjana }; 62146680fe9SYassine Oudjana }; 62246680fe9SYassine Oudjana 623372698e8SKrzysztof Kozlowski regulators-1 { 62446680fe9SYassine Oudjana compatible = "qcom,rpm-pmi8994-regulators"; 62546680fe9SYassine Oudjana 62646680fe9SYassine Oudjana vdd_s1-supply = <&vph_pwr>; 62746680fe9SYassine Oudjana vdd_s2-supply = <&vph_pwr>; 62846680fe9SYassine Oudjana vdd_s3-supply = <&vph_pwr>; 62946680fe9SYassine Oudjana vdd_bst_byp-supply = <&vph_pwr>; 63046680fe9SYassine Oudjana 63146680fe9SYassine Oudjana vreg_s1b_1p025: s1 { 63246680fe9SYassine Oudjana regulator-name = "vreg_s1b_1p025"; 63346680fe9SYassine Oudjana regulator-min-microvolt = <1025000>; 63446680fe9SYassine Oudjana regulator-max-microvolt = <1025000>; 63546680fe9SYassine Oudjana }; 63646680fe9SYassine Oudjana 63746680fe9SYassine Oudjana vph_pwr_bbyp: boost-bypass { 63846680fe9SYassine Oudjana regulator-name = "vph_pwr_bbyp"; 63946680fe9SYassine Oudjana regulator-min-microvolt = <3150000>; 64046680fe9SYassine Oudjana regulator-max-microvolt = <3600000>; 64146680fe9SYassine Oudjana }; 64246680fe9SYassine Oudjana }; 64346680fe9SYassine Oudjana}; 64446680fe9SYassine Oudjana 64546680fe9SYassine Oudjana&pm8994_spmi_regulators { 64646680fe9SYassine Oudjana qcom,saw-reg = <&saw3>; 64746680fe9SYassine Oudjana s8 { 64846680fe9SYassine Oudjana qcom,saw-slave; 64946680fe9SYassine Oudjana }; 65046680fe9SYassine Oudjana s9 { 65146680fe9SYassine Oudjana qcom,saw-slave; 65246680fe9SYassine Oudjana }; 65346680fe9SYassine Oudjana s10 { 65446680fe9SYassine Oudjana qcom,saw-slave; 65546680fe9SYassine Oudjana }; 65646680fe9SYassine Oudjana vreg_apc_0p8: s11 { 65746680fe9SYassine Oudjana qcom,saw-leader; 65846680fe9SYassine Oudjana regulator-name = "vreg_apc_0p8"; 65946680fe9SYassine Oudjana regulator-min-microvolt = <470000>; 66046680fe9SYassine Oudjana regulator-max-microvolt = <1140000>; 66146680fe9SYassine Oudjana regulator-max-step-microvolt = <150000>; 66246680fe9SYassine Oudjana regulator-always-on; 66346680fe9SYassine Oudjana }; 66446680fe9SYassine Oudjana}; 66546680fe9SYassine Oudjana 66646680fe9SYassine Oudjana&pmi8994_spmi_regulators { 66746680fe9SYassine Oudjana vdd_gfx: s2 { 66846680fe9SYassine Oudjana regulator-name = "vdd_gfx"; 66946680fe9SYassine Oudjana regulator-min-microvolt = <400000>; 67046680fe9SYassine Oudjana regulator-max-microvolt = <1015000>; 67146680fe9SYassine Oudjana regulator-enable-ramp-delay = <500>; 67246680fe9SYassine Oudjana }; 67346680fe9SYassine Oudjana}; 67446680fe9SYassine Oudjana 67546680fe9SYassine Oudjana&pm8994_gpios { 676b94d7c1fSKrzysztof Kozlowski irled_default: irled-default-state { 677d710fdfeSYassine Oudjana pins = "gpio5"; 678d710fdfeSYassine Oudjana function = PMIC_GPIO_FUNC_FUNC1; 679d710fdfeSYassine Oudjana output-low; 680d710fdfeSYassine Oudjana qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; 681d710fdfeSYassine Oudjana power-source = <PM8994_GPIO_S4>; 682d710fdfeSYassine Oudjana bias-disable; 683d710fdfeSYassine Oudjana }; 684d710fdfeSYassine Oudjana 685ff36bed5SKrzysztof Kozlowski wlan_en_default: wlan-en-state { 68646680fe9SYassine Oudjana pins = "gpio8"; 68746680fe9SYassine Oudjana function = PMIC_GPIO_FUNC_NORMAL; 68846680fe9SYassine Oudjana output-low; 68946680fe9SYassine Oudjana qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; 69046680fe9SYassine Oudjana power-source = <PM8994_GPIO_S4>; 69146680fe9SYassine Oudjana bias-disable; 69246680fe9SYassine Oudjana }; 69346680fe9SYassine Oudjana 694ff36bed5SKrzysztof Kozlowski rome_enable_default: rome-enable-state { 69546680fe9SYassine Oudjana pins = "gpio9"; 69646680fe9SYassine Oudjana function = PMIC_GPIO_FUNC_NORMAL; 69746680fe9SYassine Oudjana output-high; 69846680fe9SYassine Oudjana qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; 69946680fe9SYassine Oudjana power-source = <PM8994_GPIO_VPH>; 70046680fe9SYassine Oudjana }; 70146680fe9SYassine Oudjana 702ff36bed5SKrzysztof Kozlowski divclk1_default: divclk1-state { 70346680fe9SYassine Oudjana pins = "gpio15"; 70446680fe9SYassine Oudjana function = PMIC_GPIO_FUNC_FUNC1; 70546680fe9SYassine Oudjana bias-disable; 70646680fe9SYassine Oudjana power-source = <PM8994_GPIO_S4>; 70746680fe9SYassine Oudjana qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; 70846680fe9SYassine Oudjana }; 70946680fe9SYassine Oudjana 710ff36bed5SKrzysztof Kozlowski divclk4_pin_a: divclk4-state { 71146680fe9SYassine Oudjana pins = "gpio18"; 71246680fe9SYassine Oudjana function = PMIC_GPIO_FUNC_FUNC2; 71346680fe9SYassine Oudjana bias-disable; 71446680fe9SYassine Oudjana power-source = <PM8994_GPIO_S4>; 71546680fe9SYassine Oudjana }; 71646680fe9SYassine Oudjana}; 71746680fe9SYassine Oudjana 71846680fe9SYassine Oudjana&tlmm { 719169e1553SKrzysztof Kozlowski mdss_dsi_default: mdss-dsi-default-state { 72046680fe9SYassine Oudjana pins = "gpio8"; 72146680fe9SYassine Oudjana function = "gpio"; 72246680fe9SYassine Oudjana drive-strength = <8>; 72346680fe9SYassine Oudjana bias-disable; 72446680fe9SYassine Oudjana }; 72546680fe9SYassine Oudjana 726169e1553SKrzysztof Kozlowski mdss_dsi_sleep: mdss-dsi-sleep-state { 72746680fe9SYassine Oudjana pins = "gpio8"; 72846680fe9SYassine Oudjana function = "gpio"; 72946680fe9SYassine Oudjana drive-strength = <2>; 73046680fe9SYassine Oudjana bias-pull-down; 73146680fe9SYassine Oudjana }; 73246680fe9SYassine Oudjana 733169e1553SKrzysztof Kozlowski mdss_te_default: mdss-te-default-state { 73446680fe9SYassine Oudjana pins = "gpio10"; 73546680fe9SYassine Oudjana function = "mdp_vsync"; 73646680fe9SYassine Oudjana drive-strength = <2>; 73746680fe9SYassine Oudjana bias-pull-down; 73846680fe9SYassine Oudjana }; 73946680fe9SYassine Oudjana 740169e1553SKrzysztof Kozlowski mdss_te_sleep: mdss-te-sleep-state { 74146680fe9SYassine Oudjana pins = "gpio10"; 74246680fe9SYassine Oudjana function = "mdp_vsync"; 74346680fe9SYassine Oudjana drive-strength = <2>; 74446680fe9SYassine Oudjana bias-pull-down; 74546680fe9SYassine Oudjana }; 74646680fe9SYassine Oudjana 747169e1553SKrzysztof Kozlowski nfc_default: nfc-default-state { 74846680fe9SYassine Oudjana pins = "gpio12", "gpio21"; 74946680fe9SYassine Oudjana function = "gpio"; 75046680fe9SYassine Oudjana drive-strength = <16>; 75146680fe9SYassine Oudjana bias-pull-up; 75246680fe9SYassine Oudjana }; 75346680fe9SYassine Oudjana}; 754