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/openbmc/qemu/util/
H A Dqemu-thread-win32.c10 * See the COPYING file in the top-level directory.
17 #include "qemu-thread-common.h"
70 InitializeSRWLock(&mutex->lock); in qemu_mutex_init()
76 assert(mutex->initialized); in qemu_mutex_destroy()
77 mutex->initialized = false; in qemu_mutex_destroy()
78 InitializeSRWLock(&mutex->lock); in qemu_mutex_destroy()
83 assert(mutex->initialized); in qemu_mutex_lock_impl()
85 AcquireSRWLockExclusive(&mutex->lock); in qemu_mutex_lock_impl()
93 assert(mutex->initialized); in qemu_mutex_trylock_impl()
94 owned = TryAcquireSRWLockExclusive(&mutex->lock); in qemu_mutex_trylock_impl()
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H A Dqemu-thread-posix.c10 * See the COPYING file in the top-level directory.
17 #include "qemu-thread-common.h"
56 static void compute_abs_deadline(struct timespec *ts, int ms) in compute_abs_deadline() argument
59 ts->tv_nsec += (ms % 1000) * 1000000; in compute_abs_deadline()
60 ts->tv_sec += ms / 1000; in compute_abs_deadline()
61 if (ts->tv_nsec >= 1000000000) { in compute_abs_deadline()
62 ts->tv_sec++; in compute_abs_deadline()
63 ts->tv_nsec -= 1000000000; in compute_abs_deadline()
71 err = pthread_mutex_init(&mutex->lock, NULL); in qemu_mutex_init()
81 assert(mutex->initialized); in qemu_mutex_destroy()
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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dintel-gw-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rtanwar@maxlinear.com>
16 const: intel,lgm-pcie
18 - compatible
21 - $ref: /schemas/pci/snps,dw-pcie.yaml#
26 - const: intel,lgm-pcie
27 - const: snps,dw-pcie
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/openbmc/qemu/hw/s390x/
H A Ds390-virtio-ccw.c10 * your option) any later version. See the COPYING file in the top-level
17 #include "system/confidential-guest-support.h"
21 #include "virtio-ccw.h"
22 #include "qemu/config-file.h"
24 #include "qemu/error-report.h"
26 #include "qemu/qemu-print.h"
28 #include "hw/s390x/s390-pci-bus.h"
29 #include "system/reset.h"
30 #include "hw/s390x/storage-keys.h"
31 #include "hw/s390x/storage-attributes.h"
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/openbmc/linux/lib/zstd/compress/
H A Dzstd_compress.c5 * This source code is licensed under both the BSD-style license (found in the
8 * You may select, at your option, one of the above-listed licenses.
11 /*-*************************************
43 * Maximum size of the hash table dedicated to find 3-bytes matches,
54 /*-*************************************
59 * full-block strategy.
69 /*-*************************************
84 … * row-based matchfinder. Unless the cdict is reloaded, we will use
96 assert(cctx != NULL); in ZSTD_initCCtx()
98 cctx->customMem = memManager; in ZSTD_initCCtx()
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/openbmc/linux/Documentation/devicetree/bindings/rtc/
H A Dingenic,rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs Real-Time Clock
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: rtc.yaml#
14 - if:
20 - ingenic,jz4770-rtc
21 - ingenic,jz4780-rtc
24 "#clock-cells": false
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/openbmc/openbmc/meta-nvidia/meta-gb200nvl-obmc/recipes-nvidia/platform-init/files/
H A Dplatform_init.cpp1 // SPDX-License-Identifier: Apache-2.0
2 // SPDX-FileCopyrightText: 2025 NVIDIA
6 #include <systemd/sd-daemon.h>
35 std::chrono::milliseconds find_timeout = 0ms) { in set_gpio()
37 std::chrono::milliseconds polling_time = 10ms; in set_gpio()
47 find_timeout -= polling_time; in set_gpio()
75 return -1; in get_gpio()
116 value ? "assert" : "deassert"); in wait()
135 std::format("/sys/bus/platform/drivers/aspeed-i2c-bus/unbind", number); in rebind_i2c()
151 std::format("/sys/bus/platform/drivers/aspeed-i2c-bus/bind", number); in rebind_i2c()
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/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dreset_manager_arria10.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2017 Intel Corporation
62 /* Disable the watchdog (toggle reset to watchdog) */
65 /* assert reset for watchdog */ in socfpga_watchdog_disable()
66 setbits_le32(&reset_manager_base->per1modrst, in socfpga_watchdog_disable()
70 /* Release NOC ddr scheduler from reset */
73 clrbits_le32(&reset_manager_base->brgmodrst, in socfpga_reset_deassert_noc_ddr_scheduler()
85 return fdtdec_get_uint(blob, node, "init-val", 0); in get_bridge_init_val()
95 if (get_bridge_init_val(gd->fdt_blob, in socfpga_reset_deassert_bridges_handoff()
103 setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc); in socfpga_reset_deassert_bridges_handoff()
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/openbmc/linux/drivers/pci/controller/
H A Dpcie-rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
22 #include <linux/reset.h>
25 #include "pcie-rockchip.h"
29 struct device *dev = rockchip->dev; in rockchip_pcie_parse_dt()
31 struct device_node *node = dev->of_node; in rockchip_pcie_parse_dt()
35 if (rockchip->is_rc) { in rockchip_pcie_parse_dt()
38 "axi-base"); in rockchip_pcie_parse_dt()
39 rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs); in rockchip_pcie_parse_dt()
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/openbmc/u-boot/doc/
H A DREADME.i2c4 While I2C supports multi-master buses this is difficult to get right.
6 Clock-stretching and the arbitrary time that an I2C transaction can take
8 When one or more masters can be reset independently part-way through a
11 U-Boot provides a scheme based on two 'claim' GPIOs, one driven by the
18 Since U-Boot runs on the AP, the terminology used is 'our' claim GPIO,
23 i2c-arb-gpio-challenge for the implementation.
28 - AP_CLAIM: output from AP, signalling to the EC that the AP wants the bus
29 - EC_CLAIM: output from EC, signalling to the AP that the EC wants the bus
31 The basic algorithm is to assert your line when you want the bus, then make
50 To release the bus, just de-assert the claim line.
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/openbmc/linux/drivers/scsi/
H A Dmesh.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
5 * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
11 * Apr. 21 2002 - BenH Rework bus reset code for new error handler
12 * Add delay after initial bus reset
15 * Sep. 27 2003 - BenH Move to new driver model, fix some write posting
18 * - handle aborts correctly
19 * - retry arbitration if lost (unless higher levels do this for us)
20 * - power down the chip when no device is detected
76 MODULE_PARM_DESC(init_reset_delay, "Initial bus reset delay (0=no reset)");
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/openbmc/qemu/tests/functional/
H A Dtest_virtio_balloon.py3 # virtio-balloon tests
6 # later. See the COPYING file in the top-level directory.
31 '/31/Cloud/x86_64/images/Fedora-Cloud-Base-31-1.9.x86_64.qcow2'),
41 failure_message="Kernel panic - not syncing",
50 # Synchronize on virtio-block driver creating the root device
52 "while ! (dmesg -c | grep vda:) ; do sleep 1 ; done",
59 exec_command_and_wait_for_pattern(self, "modprobe virtio-balloon",
63 ret = self.vm.qmp('qom-get',
65 'property': 'guest-stats'})['return']
66 when = ret.get('last-update')
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/openbmc/u-boot/arch/x86/cpu/quark/
H A Dquark.c1 // SPDX-License-Identifier: GPL-2.0+
46 mask = ~(CONFIG_SYS_MONITOR_LEN - 1); in quark_setup_mtrr()
54 mask = ~(ESRAM_SIZE - 1); in quark_setup_mtrr()
70 /* GPIO - D31:F0:R44h */ in quark_setup_bars()
74 /* ACPI PM1 Block - D31:F0:R48h */ in quark_setup_bars()
78 /* GPE0 - D31:F0:R4Ch */ in quark_setup_bars()
82 /* WDT - D31:F0:R84h */ in quark_setup_bars()
86 /* RCBA - D31:F0:RF0h */ in quark_setup_bars()
90 /* ACPI P Block - Msg Port 04:R70h */ in quark_setup_bars()
94 /* SPI DMA - Msg Port 04:R7Ah */ in quark_setup_bars()
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/openbmc/qemu/hw/arm/
H A Dboot.c4 * Copyright (c) 2006-2007 CodeSourcery.
12 #include "qemu/error-report.h"
16 #include "hw/arm/linux-boot-if.h"
22 #include "system/reset.h"
26 #include "qemu/config-file.h"
54 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) { in arm_boot_address_space()
64 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */
68 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */
70 { 0, FIXUP_ARGPTR_LO }, /* arg: .word @DTB Lower 32-bits */
71 { 0, FIXUP_ARGPTR_HI}, /* .word @DTB Higher 32-bits */
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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dti,tas5086.txt1 Texas Instruments TAS5086 6-channel PWM Processor
5 - compatible: Should contain "ti,tas5086".
6 - reg: The i2c address. Should contain <0x1b>.
10 - reset-gpio: A GPIO spec to define which pin is connected to the
11 chip's !RESET pin. If specified, the driver will
12 assert a hardware reset at probe time.
14 - ti,charge-period: This property should contain the time in microseconds
15 that closely matches the external single-ended
16 split-capacitor charge period. The hardware chip
20 When not specified, the hardware default of 1300ms
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/openbmc/u-boot/arch/arm/cpu/armv7/sunxi/
H A Dpsci.c1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Chen-Yu Tsai <wens@csie.org>
7 * which was based on code by Carl van Schaik <carl@ok-labs.com>.
32 * The power clamps are located in the unused space after the per-core
33 * reset controls for core 3. The secondary core entry address register
61 static void __secure __mdelay(u32 ms) in __mdelay() argument
63 u32 reg = ONE_MS * ms; in __mdelay()
133 writel((u32)entry, &cpucfg->priv0); in sunxi_set_entry_address()
144 sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff, in sunxi_cpu_set_power()
163 sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff, in sunxi_cpu_set_power()
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/openbmc/u-boot/board/Synology/ds109/
H A Dopenocd.cfg7 ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010
8 ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040
12 # length of reset signal: [ms]
15 # don't talk to JTAG after reset for: [ms]
24 # We need to assert DBGRQ while holding nSRST down.
29 # re-examine the target again here when nSRST is asserted which
36 #reset run
111 # load u-Boot into RAM and execute it
113 load_image u-boot.bin 0x00600000 bin
/openbmc/linux/drivers/gpu/drm/panel/
H A Dpanel-samsung-s6d27a1.c1 // SPDX-License-Identifier: GPL-2.0
4 * Found in the Samsung Galaxy Ace 2 GT-I8160 mobile phone.
15 #include <linux/media-bus-format.h>
46 struct gpio_desc *reset; member
76 struct mipi_dbi *dbi = &ctx->dbi; in s6d27a1_read_mtp_id()
82 dev_err(ctx->dev, "unable to read MTP ID 1\n"); in s6d27a1_read_mtp_id()
87 dev_err(ctx->dev, "unable to read MTP ID 2\n"); in s6d27a1_read_mtp_id()
92 dev_err(ctx->dev, "unable to read MTP ID 3\n"); in s6d27a1_read_mtp_id()
95 dev_info(ctx->dev, "MTP ID: %02x %02x %02x\n", id1, id2, id3); in s6d27a1_read_mtp_id()
100 struct mipi_dbi *dbi = &ctx->dbi; in s6d27a1_power_on()
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H A Dpanel-samsung-db7430.c1 // SPDX-License-Identifier: GPL-2.0
5 * Found in the Samsung Galaxy Beam GT-I8350 mobile phone.
16 #include <linux/media-bus-format.h>
49 * struct db7430 - state container for a panel controlled by the DB7430
59 /** @reset: reset GPIO line */
60 struct gpio_desc *reset; member
91 struct mipi_dbi *dbi = &db->dbi; in db7430_power_on()
95 ret = regulator_bulk_enable(ARRAY_SIZE(db->regulators), in db7430_power_on()
96 db->regulators); in db7430_power_on()
98 dev_err(db->dev, "failed to enable regulators: %d\n", ret); in db7430_power_on()
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/openbmc/linux/drivers/rtc/
H A Drtc-jz4740.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/clk-provider.h>
75 return readl(rtc->base + reg); in jz4740_rtc_reg_read()
82 return readl_poll_timeout(rtc->base + JZ_REG_RTC_CTRL, ctrl, in jz4740_rtc_wait_write_ready()
95 writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
97 return readl_poll_timeout(rtc->base + JZ_REG_RTC_WENR, ctrl, in jz4780_rtc_enable_write()
106 if (rtc->type >= ID_JZ4760) in jz4740_rtc_reg_write()
111 writel(val, rtc->base + reg); in jz4740_rtc_reg_write()
123 spin_lock_irqsave(&rtc->lock, flags); in jz4740_rtc_ctrl_set_bits()
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/openbmc/qemu/hw/core/
H A Dmachine.c10 * See the COPYING file in the top-level directory.
19 #include "qemu/error-report.h"
21 #include "qapi/qapi-visit-machine.h"
22 #include "qapi/qapi-commands-machine.h"
27 #include "system/reset.h"
34 #include "system/confidential-guest-support.h"
35 #include "hw/virtio/virtio-pci.h"
36 #include "hw/virtio/virtio-net.h"
37 #include "hw/virtio/virtio-iommu.h"
41 {"arm-cpu", "backcompat-pauth-default-use-qarma5", "true"},
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/openbmc/linux/drivers/net/wireless/intersil/orinoco/
H A Dorinoco_pci.c4 * (i.e. these are not PCMCIA cards in a PCMCIA-to-PCI bridge).
14 * Some of this code is "inspired" by linux-wlan-ng-0.1.10, but nothing
15 * has been copied from it. linux-wlan-ng-0.1.10 is originally :
20 * (C) Copyright David Gibson, IBM Corp. 2002-2003.
59 /* Bitmask to reset the card */
62 /* Magic timeouts for doing the reset.
63 * Those times are straight from wlan-ng, and it is claimed that they
65 #define HERMES_PCI_COR_ONT (250) /* ms */
66 #define HERMES_PCI_COR_OFFT (500) /* ms */
67 #define HERMES_PCI_COR_BUSYT (500) /* ms */
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/openbmc/qemu/hw/loongarch/
H A Dvirt.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #include "hw/char/serial-mm.h"
18 #include "system/reset.h"
21 #include "exec/address-spaces.h"
30 #include "hw/pci-host/ls7a.h"
31 #include "hw/pci-host/gpex.h"
36 #include "qapi/qapi-visit-common.h"
39 #include "hw/platform-bus.h"
41 #include "hw/uefi/var-service-api.h"
42 #include "hw/mem/pc-dimm.h"
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/openbmc/qemu/hw/hppa/
H A Dmachine.c3 * (C) Copyright 2018-2023 Helge Deller <deller@gmx.de>
13 #include "qemu/error-report.h"
14 #include "system/reset.h"
20 #include "hw/char/serial-mm.h"
29 #include "hw/pci-host/astro.h"
30 #include "hw/pci-host/dino.h"
40 #define HPA_POWER_BUTTON (FIRMWARE_END - 0x10)
99 NULL, "isa-io", 0x800); in hppa_isa_bus()
138 rtc_ref = val - time(NULL); in io_cpu_write()
144 qemu_chr_fe_write_all(debugout->be, &ch, 1); in io_cpu_write()
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/openbmc/qemu/hw/ppc/
H A Dspapr.c4 * Copyright (c) 2004-2007 Fabrice Bellard
7 * Copyright (c) 2010-2024, IBM Corporation..
9 * SPDX-License-Identifier: GPL-2.0-or-later
33 #include "qemu/guest-random.h"
35 #include "qapi/qapi-events-machine.h"
36 #include "qapi/qapi-events-qdev.h"
43 #include "system/reset.h"
46 #include "hw/fw-path-provider.h"
54 #include "migration/qemu-file-types.h"
58 #include "mmu-hash64.h"
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