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/openbmc/u-boot/arch/arm/dts/
H A Darmada-388-gp.dts3 * (RD-88F6820-GP)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * This file is dual-licensed: you can use it either under the terms
42 /dts-v1/;
43 #include "armada-388.dtsi"
44 #include <dt-bindings/gpio/gpio.h>
48 compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";
51 stdout-path = "serial0:115200n8";
69 internal-regs {
71 pinctrl-names = "default";
[all …]
H A Dsun9i-a80-optimus.dts2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 /dts-v1/;
46 #include "sun9i-a80.dtsi"
48 #include <dt-bindings/gpio/gpio.h>
52 compatible = "merrii,a80-optimus", "allwinner,sun9i-a80";
60 stdout-path = "serial0:115200n8";
64 compatible = "gpio-leds";
83 reg_usb1_vbus: usb1-vbus {
[all …]
H A Dsun9i-a80-cubieboard4.dts5 * Chen-Yu Tsai <wens@csie.org>
7 * This file is dual-licensed: you can use it either under the terms
46 /dts-v1/;
47 #include "sun9i-a80.dtsi"
49 #include <dt-bindings/gpio/gpio.h>
53 compatible = "cubietech,a80-cubieboard4", "allwinner,sun9i-a80";
60 stdout-path = "serial0:115200n8";
64 compatible = "gpio-leds";
77 vga-connector {
78 compatible = "vga-connector";
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/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-388-gp.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * (RD-88F6820-GP)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 /dts-v1/;
12 #include "armada-388.dtsi"
13 #include <dt-bindings/gpio/gpio.h>
16 model = "Marvell Armada 388 DB-88F6820-GP";
17 compatible = "marvell,a388-gp", "marvell,armada388", "marvell,armada380";
20 stdout-path = "serial0:115200n8";
35 internal-regs {
[all …]
H A Darmada-385-synology-ds116.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include "armada-385.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
14 compatible = "marvell,a385-gp", "marvell,armada385", "marvell,armada380";
17 stdout-path = "serial0:115200n8";
32 internal-regs {
34 pinctrl-names = "default";
35 pinctrl-0 = <&i2c0_pins>;
37 clock-frequency = <100000>;
[all …]
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-platform-dptf4 Contact: linux-acpi@vger.kernel.org
6 (RO) The charger type - Traditional, Hybrid or NVDC.
11 Contact: linux-acpi@vger.kernel.org
19 Contact: linux-acpi@vger.kernel.org
27 Contact: linux-acpi@vger.kernel.org
33 - 0x00 = DC
34 - 0x01 = AC
35 - 0x02 = USB
36 - 0x03 = Wireless Charger
43 Contact: linux-acpi@vger.kernel.org
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/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dmax8660.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/max8660.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Maxim MAX8660 voltage regulator
10 - Daniel Mack <zonque@gmail.com>
14 pattern: "pmic@[0-9a-f]{1,2}"
17 - maxim,max8660
18 - maxim,max8661
27 "^regulator-.+$":
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/openbmc/linux/drivers/regulator/
H A Dpcap-regulator.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PCAP2 Regulator Driver
13 #include <linux/regulator/driver.h>
14 #include <linux/regulator/machine.h>
15 #include <linux/mfd/ezx-pcap.h>
113 /* V5 STBY and LOWPWR are on PCAP_REG_VREG2 */
114 VREG_INFO(V5, PCAP_REG_VREG1, 15, 16, 12, 19),
147 /* the regulator doesn't support voltage switching */ in pcap_regulator_set_voltage_sel()
148 if (rdev->desc->n_voltages == 1) in pcap_regulator_set_voltage_sel()
149 return -EINVAL; in pcap_regulator_set_voltage_sel()
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/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dapq8016-sbc-d3-camera-mezzanine.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 /dts-v1/;
9 #include "apq8016-sbc.dts"
12 camera_vdddo_1v8: camera-vdddo-1v8 {
13 compatible = "regulator-fixed";
14 regulator-name = "camera_vdddo";
15 regulator-min-microvolt = <1800000>;
16 regulator-max-microvolt = <1800000>;
17 regulator-always-on;
20 camera_vdda_2v8: camera-vdda-2v8 {
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/dac/
H A Dti,dac082s085.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 A family of Texas Instruments 8/10/12-bit 2/4-channel DACs
13 - Lukas Wunner <lukas@wunner.de>
18 - ti,dac082s085
19 - ti,dac102s085
20 - ti,dac122s085
21 - ti,dac084s085
22 - ti,dac104s085
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-emcon-avari.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
15 stdout-path = &uart1;
18 reg_wall_5p0: regulator-wall5p0 {
19 compatible = "regulator-fixed";
20 regulator-name = "Main-Supply";
21 regulator-min-microvolt = <5000000>;
22 regulator-max-microvolt = <5000000>;
23 regulator-always-on;
24 regulator-boot-on;
27 reg_base3p3: regulator-base3p3 {
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H A Dimx8mq-nitrogen.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
13 compatible = "boundary,imx8mq-nitrogen8m", "fsl,imx8mq";
16 stdout-path = "serial0:115200n8";
24 gpio-keys {
25 compatible = "gpio-keys";
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_gpio_keys>;
29 button-power {
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/openbmc/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa300-raumfeld-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
10 hw-revision = <0>;
14 stdout-path = &ffuart;
22 reg_3v3: regulator-3v3 {
23 compatible = "regulator-fixed";
24 regulator-name = "3v3-fixed-supply";
25 regulator-min-microvolt = <3300000>;
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-emcon-avari.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
15 reg_wall_5p0: reg-wall5p0 {
16 compatible = "regulator-fixed";
17 regulator-name = "Main-Supply";
18 regulator-min-microvolt = <5000000>;
19 regulator-max-microvolt = <5000000>;
20 regulator-always-on;
21 regulator-boot-on;
24 reg_base3p3: reg-base3p3 {
25 compatible = "regulator-fixed";
[all …]
H A Dimx53-tx53.dtsi2 * Copyright 2012-2017 <LW@KARO-electronics.de>
3 * based on imx53-qsb.dts
7 * This file is dual-licensed: you can use it either under the terms
46 #include <dt-bindings/gpio/gpio.h>
49 model = "Ka-Ro electronics TX53 module";
62 reg-can-xcvr = &reg_can_xcvr;
69 clock-frequency = <0>;
73 mclk: clock-mclk {
74 compatible = "fixed-clock";
75 #clock-cells = <0>;
[all …]
H A Dimx6ul-tx6ul.dtsi2 * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
4 * This file is dual-licensed: you can use it either under the terms
42 #include <dt-bindings/gpio/gpio.h>
43 #include <dt-bindings/interrupt-controller/irq.h>
44 #include <dt-bindings/pwm/pwm.h>
56 lcdif-23bit-pins-a = &pinctrl_disp0_1;
57 lcdif-24bit-pins-a = &pinctrl_disp0_2;
59 reg-can-xcvr = &reg_can_xcvr;
70 stdout-path = &uart1;
75 reg = <0x80000000 0>; /* will be filled by U-Boot */
[all …]
H A Dimx6qdl-tx6.dtsi2 * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de>
4 * This file is dual-licensed: you can use it either under the terms
42 #include <dt-bindings/gpio/gpio.h>
43 #include <dt-bindings/input/input.h>
44 #include <dt-bindings/interrupt-controller/irq.h>
45 #include <dt-bindings/pwm/pwm.h>
46 #include <dt-bindings/sound/fsl-imx-audmux.h>
53 lcdif-23bit-pins-a = &pinctrl_disp0_1;
54 lcdif-24bit-pins-a = &pinctrl_disp0_2;
57 reg-can-xcvr = &reg_can_xcvr;
[all …]
H A Dimx6dl-b1x5pv2.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 // Copyright 2018-2021 General Electric Company
7 // Copyright 2018-2021 Collabora
9 #include <dt-bindings/input/input.h>
10 #include "imx6dl-qmx6.dtsi"
14 stdout-path = &uart3;
20 operating-points = <
25 fsl,soc-operating-points = <
26 /* ARM kHz SOC-PU uV */
33 operating-points = <
[all …]
/openbmc/linux/drivers/ufs/host/
H A Dufs-mediatek.h1 /* SPDX-License-Identifier: GPL-2.0 */
53 * Ref-clk control
143 struct regulator *reg_vcore;
171 struct regulator *reg_va09;
194 * Multi-VCC by Numbering
221 unsigned long v5; member
229 s.cmd, s.v1, s.v2, s.v3, s.v4, s.v5, s.v6, s.res); in _ufs_mtk_smc()
/openbmc/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a-iot.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2021-2022 NXP
7 /dts-v1/;
11 model = "LS1021A-IOT Board";
12 compatible = "fsl,ls1021a-iot", "fsl,ls1021a";
14 sys_mclk: clock-mclk {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <24576000>;
20 reg_3p3v: regulator-3V3 {
[all …]
H A Dls1021a-tsn.dts1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2016-2018 NXP Semiconductors
6 /dts-v1/;
10 model = "NXP LS1021A-TSN Board";
11 compatible = "fsl,ls1021a-tsn", "fsl,ls1021a";
13 sys_mclk: clock-mclk {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <24576000>;
19 reg_vdda_codec: regulator-3V3 {
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3066a-mk808.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/input.h>
20 stdout-path = "serial2:115200n8";
28 adc-keys {
29 compatible = "adc-keys";
30 io-channels = <&saradc 1>;
31 io-channel-names = "buttons";
32 keyup-threshold-microvolt = <2500000>;
33 poll-interval = <100>;
[all …]
/openbmc/linux/sound/soc/amd/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 select REGULATOR
39 tristate "AMD Audio Coprocessor-v3.x support"
58 tristate "AMD Audio Coprocessor - Renoir support"
72 tristate "AMD Audio Coprocessor-v5.x I2S support"
76 This option enables ACP v5.x support on AMD platform
95 tristate "AMD Audio Coprocessor-v6.x Yellow Carp support"
126 tristate "AMD Audio Coprocessor-v6.2 RPL support"
136 tristate "AMD Audio Coprocessor-v6.3 Pink Sardine support"
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am64-phycore-som.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
10 * https://www.phytec.com/product/phycore-am64x
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/net/ti-dp83867.h>
18 model = "PHYTEC phyCORE-AM64x";
19 compatible = "phytec,am64-phycore-som", "ti,am642";
32 reserved-memory {
33 #address-cells = <2>;
[all …]
/openbmc/linux/include/linux/mfd/
H A Dezx-pcap.h1 /* SPDX-License-Identifier: GPL-2.0 */
54 #define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */
55 #define PCAP_REG_AUXVREG 0x7 /* Auxiliary Regulator Control */
64 #define PCAP_REG_LOWPWR 0x18 /* Regulator Low Power Control */
74 #define PCAP_REG_SWCTRL 0x4 /* Switching Regulator Control */
75 #define PCAP_REG_VREG1 0x5 /* Regulator Bank 1 Control */
82 #define PCAP_REG_AUXVREG_MASK 0x16 /* Auxiliary Regulator Mask */
117 #define V5 4 macro

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